Reducing power dissipation for solid state disks

• US 20080235441A1
• Filed: 10/22/2007
• Published: 09/25/2008
• Est. Priority Date: 03/20/2007
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Sherman, Itay
• Application Number:
  US11/975,854
• Publication Number:
  US 20080235441A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A data processing device including a computer, the computer including a solid state disk (SSD), including a primary memory for single level cell storage, and a secondary memory for multi-level cell storage, a limited internal battery for supplying power to the computer, a socket for connecting the computer to an external power supply source, a detector for indicating that the computer is connected to an external power source, a processor for transferring data from the primary memory to the secondary memory, and an SSD controller for deciding whether or not the processor may transfer data from the primary memory to the secondary memory, based on a signal received from said detector. A method for SSD memory management is also described and claimed.

Claims

1. A data processing device comprising a computer, the computer comprising:

a solid state disk (SSD), comprising;

a primary memory for single level cell storage; and

a secondary memory for multi-level cell storage;

a limited internal battery for supplying power to said computer;

a socket for connecting said computer to an external power supply source;

a detector for indicating that said computer is connected to an external power source;

a processor for transferring data from said primary memory to said secondary memory; and

an SSD controller for deciding whether or not said processor may transfer data from said primary memory to said secondary memory, based on a signal received from said detector.

2. The data processing device of claim 1 wherein said SSD controller decides whether or not said processor may transfer data from said primary memory to said secondary memory based on available free space in said primary memory.

3. The data processing device of claim 1 wherein said detector comprises a voltage monitor for monitoring the voltage level supplied to said SSD.

4. A method for solid-state disk (SSD) memory management, comprising:

providing a SSD within a computer, the SSD including a primary SSD memory for single level cell storage, and a secondary SSD memory for multi-level cell storage, wherein power may be supplied to the computer from an external power supply source or from a limited internal battery;

determining if the computer is connected to an external power source; and

if said determining determines that the computer is connected to an external power source, then enabling transfer of data from the primary SSD memory to the secondary SSD memory.

5. The method of claim 4 further comprising:

determining an amount of available free space in the primary SSD memory; and

if said determining determines that the available free space in the primary SSD memory is below a designated amount, then enabling transfer of data from the primary SSD memory to the secondary SSD memory.

6. The method of claim 4 wherein said determining comprises monitoring a voltage level supplied to the SSD.