Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels
First Claim
1. A Non-Volatile Memory Device (NVMD) comprising:
- a host-device interface for receiving commands from a host over a host bus;
a bridge, coupled to the host-device interface, for converting requests from the host into concurrent requests;
a traffic controller and dispatcher, coupled to the bridge, receiving the concurrent requests, for dispatching the concurrent requests over an internal bus;
a plurality of NVMD branches, each NVMD branch coupled to the internal bus to receive one of the concurrent requests from the traffic controller and dispatcher;
wherein each NVMD branch of the plurality of NVMD branches further comprises;
a NVMD controller, coupled to the internal bus, having control logic and a flash channel interface; and
a NVMD memory;
wherein multiple NVMD branches are accessed concurrently in parallel by the concurrent requests;
wherein the NVMD is a single chip integrated onto a single substrate of silicon;
wherein the NVMD memory in each of the NVMD branches comprises;
a memory interface coupled to the flash channel interface;
a non-volatile memory array for storing blocks of data;
a block address manager, for receiving a logical block address (LBA) from the traffic controller and dispatcher, for mapping the LBA to a physical block address (PBA) within a non-volatile memory array in the NVMD,whereby requests from the host are dispatched to multiple NVMD branches.
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Accused Products
Abstract
A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
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Citations
23 Claims
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1. A Non-Volatile Memory Device (NVMD) comprising:
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a host-device interface for receiving commands from a host over a host bus; a bridge, coupled to the host-device interface, for converting requests from the host into concurrent requests; a traffic controller and dispatcher, coupled to the bridge, receiving the concurrent requests, for dispatching the concurrent requests over an internal bus; a plurality of NVMD branches, each NVMD branch coupled to the internal bus to receive one of the concurrent requests from the traffic controller and dispatcher; wherein each NVMD branch of the plurality of NVMD branches further comprises; a NVMD controller, coupled to the internal bus, having control logic and a flash channel interface; and a NVMD memory; wherein multiple NVMD branches are accessed concurrently in parallel by the concurrent requests; wherein the NVMD is a single chip integrated onto a single substrate of silicon; wherein the NVMD memory in each of the NVMD branches comprises; a memory interface coupled to the flash channel interface; a non-volatile memory array for storing blocks of data; a block address manager, for receiving a logical block address (LBA) from the traffic controller and dispatcher, for mapping the LBA to a physical block address (PBA) within a non-volatile memory array in the NVMD, whereby requests from the host are dispatched to multiple NVMD branches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A storage system comprising:
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a connector to a host system, the connector having a host bus; a host-device interface, coupled to the connector, for interfacing to the host using a host protocol; a bridge, coupled to the host-device interface, for protocol conversion and handshaking; a traffic controller and dispatcher, coupled to the bridge and to an internal bus, for dispatching concurrent requests over the host bus for concurrent operations; a first Non-Volatile Memory Device (NVMD) branch having a first NVMD controller coupled to the internal bus and a first NVMD; a second NVMD branch having a second NVMD controller coupled to the internal bus and a second NVMD; wherein the first and second NVMD controller each comprise; a logic circuit for interfacing to the internal bus; a flash channel interface for channeling flash commands generated in response to one of the concurrent requests; wherein the first and second NVMD each comprise; a memory interface, coupled to the flash channel interface, for processing the flash commands; and a non-volatile memory array for storing blocks of data in response to the flash commands received by the memory interface, wherein concurrent requests are dispatched to the first and second NVMD branches. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A multi-level Non-Volatile Memory Device (NVMD) system comprising:
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host-device interface means for receiving commands from a host over a host bus; bridge means, coupled to the host-device interface means, for converting requests from the host into parallel requests; traffic controller and dispatch means, coupled to the bridge means, receiving the concurrent requests, for dispatching the concurrent requests over an internal bus; a plurality of NVMD branches, each NVMD branch coupled to the internal bus to receive one of the concurrent requests from the traffic controller and dispatch means; wherein each NVMD branch of the plurality of NVMD branches further comprises; NVMD controller means, coupled to the internal bus, for interfacing between the internal bus and a flash channel; a NVMD memory, having a memory interface coupled to the NVMD controller means, having a non-volatile memory array for storing blocks of data; block address manager means, for receiving a logical block address (LBA) from the traffic controller and dispatch means, and for mapping the LBA to a physical block address (PBA) within a non-volatile memory array in the NVMD memory; controller cache means for storing blocks of data for storing in the NVMD memory; high-speed cache means for buffering a block of data for storage in the NVMD memory array, wherein multiple NVMD branches are accessed concurrently in parallel by the concurrent requests; whereby serial requests from the host are converted to concurrent requests and dispatched to multiple NVMD branches. - View Dependent Claims (20, 21, 22, 23)
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Specification