ERROR CORRECTION CIRCUIT AND METHOD THEREOF
First Claim
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1. A method for error correction applied to a digital display interface Sink device at a decoding stage, the method comprising the steps of:
- determining whether a number of decoding errors of a decoding error signal is greater than a threshold value within a predetermined period of time; and
adjusting a setting value to set a physical layer while the number of decoding errors is greater than the threshold value.
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Abstract
An error correction circuit and method applicable to a DisplayPort receiver is disclosed. While decoding errors occur at a decoding stage, the invention actively adjusts settings of a physical layer by using an ANSI10B/8B decoder and performs data recovery by using a correcting unit that improves the reliability of input data.
42 Citations
20 Claims
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1. A method for error correction applied to a digital display interface Sink device at a decoding stage, the method comprising the steps of:
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determining whether a number of decoding errors of a decoding error signal is greater than a threshold value within a predetermined period of time; and adjusting a setting value to set a physical layer while the number of decoding errors is greater than the threshold value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for error correction applied to a digital display interface Sink device at a decoding stage, the method comprising the steps of:
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determining whether a number of decoding errors of a decoding error signal is greater than a threshold value within a predetermined period of time; and correcting one or a plurality of corresponding signals according to the decoding error signal while the number of decoding errors is greater than the threshold value. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An error correction circuit applied to a digital display interface Sink device, comprising:
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at least one converting circuit, each comprising; an equalizer for amplifying an differential signal and generating an amplified signal; a clock data recovery circuit for receiving the amplified signal and generating a recovered data; a serial to parallel converter for generating a parallel data according to the recovered data and; and a decoder for generating a decoded data, a decoding control signal, a decoding error signal or selected combinations thereof according to the parallel data; and a microprocessor for adjusting the equalizer, the clock data recovery circuit or both according to the decoding error signal if a number of decoding errors of the decoding error signal is greater than a threshold value within a predetermined period of time. - View Dependent Claims (18, 19, 20)
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Specification