Plasma Processing Apparatus

• US 20080236751A1
• Filed: 08/24/2007
• Published: 10/02/2008
• Est. Priority Date: 03/30/2007
• Status: Abandoned Application

• Current Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Nishio, Ryoji, Aramaki, Tooru
• Application Number:
  US11/844,377
• Publication Number:
  US 20080236751A1
• Time in Patent Office: Days
• US Class Current: 156/345.43
• CPC Class Codes: H01J 37/32192 Microwave generated discharge H01J37/32357, H01J37/32366, H01J37/32394, H01J37/32403 take precedence
• CPC Class Codes: H01J 37/32568 Relative arrangement or disposition of electrodes; moving means
• CPC Class Codes: H01J 37/32642 Focus rings
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks

Abstract

A plasma processing apparatus wherein a layer structure consisting of plural layers formed in stack one upon another on a semiconductor wafer placed on the sample holder located in the process chamber, is etched with plasma generated in the process chamber by supplying high frequency power to the electrode disposed in the sample holder, the apparatus comprising a ring-shaped electrode disposed above the electrode and around the periphery of the top portion of the sample holder, an outer circumferential ring of dielectric material disposed above the ring-shaped electrode and opposite to the plasma, and a power source for supplying power at different values to the ring-shaped electrode depending on the sorts of layers of the layer structure.

Claims

1. A plasma processing apparatus wherein a layer structure consisting of plural layers formed in stack one upon another on a semiconductor wafer placed on the sample holder located in the process chamber, is etched with plasma generated in the process chamber by supplying high frequency power to the electrode disposed in the sample holder, the apparatus comprising a ring-shaped electrode disposed above the electrode and around the periphery of the top portion of the sample holder, an outer circumferential ring of dielectric material disposed above the ring-shaped electrode and opposite to the plasma, and a power source for supplying power at different values to the ring-shaped electrode depending on the sorts of layers of the layer structure.

2. A plasma processing apparatus as claimed in claim 1, wherein the sample holder in the shape of cylinder has its top portion reduced in diameter, the surface of the top portion serving as a sample resting surface, and when the wafer is processed, inert gas is supplied into the process chamber through the gap between the outer circumferential ring and the lower surface of the outer periphery of the wafer extending in the radial direction a little beyond the periphery of the sample resting surface of the top portion of the sample holder.

3. A plasma processing apparatus as claimed in claim 1, wherein the power source supplies power having different average value to the ring-shaped electrode depending on the sorts of the layers of the layer structure of the semiconductor wafer.

4. A plasma processing apparatus as claimed in claim 1, wherein the power source supplies at least two types of power having different values to the ring-shaped electrode and supplies the two types of power in different ratios depending on the sorts of the layers of the layer structure.

5. A plasma processing apparatus as claimed in claim 1, wherein the layer structure comprises an uppermost phtoresist layer serving as mask, a layer underlying the masking layer and having a lower etching speed, and a layer underlying the layer having the lower etching speed and having a faster etching speed.

6. A plasma processing apparatus as claimed in claim 1, wherein the layer structure comprises an uppermost photoresist layer, a first layer underlying the photoresist layer and to be etched with the photoresist layer used as mask, and a second layer underlying the first layer, having an etching speed higher than the etching speed for the first layer, and to be etched with the first layer used as mask.

7. A plasma processing apparatus as claimed in claim 5, wherein the value of the power supplied to the ring-shaped electrode when the layer having the lower etching speed is processed, is made smaller than the value of the power supplied to the ring-shaped electrode when the layer having the higher etching speed is processed.

8. A plasma processing apparatus as claimed in claim 5, wherein the difference between the potential over the ring-shaped electrode and the potential over the wafer, developed when the layer having the lower etching speed is processed, is made smaller than the difference between the corresponding potentials developed when the layer having the higher etching speed is processed.

9. A plasma processing apparatus as claimed in claim 5, wherein the value of the power supplied to the ring-shaped electrode when the first layer is processed is made smaller than the value of the power supplied to the ring-shaped electrode when the second layer is processed.

10. A plasma processing apparatus as claimed in claim 5, wherein the difference between the potential over the ring-shaped electrode and the potential over the wafer, developed when the first layer is processed, is made smaller than the difference between the corresponding potentials developed when the second layer is processed.

11. A plasma processing apparatus as claimed in claim 5, wherein the amount of gas supplied into the process chamber for generating adhesive substances is less when the layer having the lower etching speed is processed than when the layer having the higher speed of etching is processed.