FORMING A TYPE I HETEROSTRUCTURE IN A GROUP IV SEMICONDUCTOR

• US 20080237572A1
• Filed: 03/27/2007
• Published: 10/02/2008
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack T., Tsai, Wilman, Majhi, Prashant, Chui, Chi On
• Granted Patent: US 7,435,987 B1
• Time in Patent Office: Days
• US Class Current: 257/14
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET

Abstract

In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si_1-xGe_x), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si_1-yGe_y(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si_1-zGe_z(C). Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a silicon (Si) substrate;

a first buffer layer formed of silicon germanium tin (SiGe(Sn)) on the Si substrate;

a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si_1-xGe_x); and

a quantum well (QW) layer including;

a lower QW barrier layer on the barrier layer, the lower QW barrier layer formed of silicon germanium carbon (Si_1-yGe_y(C));

a strained QW channel layer formed of germanium on the lower QW layer; and

an upper QW barrier layer on the strained QW channel layer formed of Si_1-zGe_z(C).

2. The apparatus of claim 1, wherein the first buffer layer is formed of Si_1-xGe_x at an interface with the Si substrate and is graded with increasing concentration of germanium (Ge) to obtain a Ge concentration of at least approximately 80%.

3. The apparatus of claim 2, wherein x is greater than y.

4. The apparatus of claim 3, wherein z is less than or equal to y.

5. The apparatus of claim 2, wherein the lower and upper QW barrier layers are tensile strained.

6. The apparatus of claim 5, where the strained QW channel layer is compressive strained.

7. The apparatus of claim 2, further comprising:

a spacer layer formed over the quantum well layer;

a delta-doped layer formed over the spacer layer; and

an upper barrier layer formed over the delta-doped layer, the upper barrier layer formed of Si_1-xGe_x.

8. The apparatus of claim 7, wherein the apparatus comprises a high electron mobility transistor (HEMT) or high hole mobility transistor (HHMT), wherein the quantum well layer comprises a channel of the HEMT or HHMT.

9. A method comprising:

forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate;

forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si_1-xGe_x); and

forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si_1-yGe_y(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si_1-zGe_z(C).

10. The method of claim 9, wherein the first buffer layer is formed of Si_1-xGe_x at an interface with the Si substrate and is graded with increasing concentration of germanium (Ge) to obtain a Ge concentration of at least approximately 80%.

11. The method of claim 10, wherein x is greater than y and z is less than or equal to y.

12. The method of claim 11, wherein the lower and upper QW barrier layers are tensile strained.

13. The method of claim 12, wherein the strained QW channel layer is compressive strained.

14. The method of claim 13, further comprising forming a high electron mobility transistor (HEMT) or a high hole mobility transistor (HHMT), wherein the quantum well layer comprises a channel of the HEMT or HHMT.