Flat panel display device and method of fabricating the same
First Claim
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1. A flat panel display device, comprising:
- a substrate including a first region on which an organic light emitting diode and a thin film transistor are formed and a second region on which a capacitor is formed;
a semiconductor layer including source and drain regions on the first region;
a first capacitor electrode formed on the second region;
a gate insulating layer formed on the substrate;
a gate electrode formed on the first region on the gate insulating layer;
a second capacitor electrode formed on the second region;
an interlayer insulating layer formed on the substrate;
source and drain electrodes formed on the first region on the interlayer insulating layer and connected with the semiconductor layer through first and second contact holes;
a first power voltage line formed on the second region connected with the second capacitor electrode through a third contact hole; and
a third capacitor electrode formed on the second region connected with the first capacitor electrode through a fourth contact hole, and having a different area from the first capacitor electrode.
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Abstract
A flat panel display device including a first region having an organic light emitting diode and a thin film transistor and a second region having a capacitor is disclosed. The capacitor comprises first, second, and third electrodes, where the area of a third capacitor electrode is reduced, thereby ensuring a distance between a first power voltage line and the third capacitor electrode. The total area of the capacitor is compensated by increasing the area of the first capacitor electrode. Thus, the area of the third capacitor electrode is reduced while the total capacitance of the capacitor is maintained, thereby preventing a dark spot caused by a short circuit between the first power voltage line and the third capacitor electrode.
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Citations
20 Claims
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1. A flat panel display device, comprising:
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a substrate including a first region on which an organic light emitting diode and a thin film transistor are formed and a second region on which a capacitor is formed; a semiconductor layer including source and drain regions on the first region; a first capacitor electrode formed on the second region; a gate insulating layer formed on the substrate; a gate electrode formed on the first region on the gate insulating layer; a second capacitor electrode formed on the second region; an interlayer insulating layer formed on the substrate; source and drain electrodes formed on the first region on the interlayer insulating layer and connected with the semiconductor layer through first and second contact holes; a first power voltage line formed on the second region connected with the second capacitor electrode through a third contact hole; and a third capacitor electrode formed on the second region connected with the first capacitor electrode through a fourth contact hole, and having a different area from the first capacitor electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of fabricating a flat panel display device, comprising:
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providing a substrate including a first region in which an organic light emitting diode and a thin film transistor are formed and a second region in which a capacitor is formed; forming a semiconductor layer on the first region on the substrate; forming a first capacitor electrode on the second region; forming a gate insulating layer on the substrate; forming a gate electrode on the first region on the gate insulating layer, forming a second capacitor electrode on the second region on the gate insulating layer; injecting a dopant into the semiconductor layer and forming source and drain regions; forming an interlayer insulating layer on the substrate; forming first and second contact holes respectively exposing the source and drain regions on the interlayer insulating layer, forming third and fourth contact holes respectively exposing the first capacitor electrode and the second capacitor electrode; forming source and drain electrodes connected with the source and drain regions through the first and second contact holes on the first region on the interlayer insulating layer; forming a first power voltage line connected with the second capacitor electrode through the third contact hole; and forming a third capacitor electrode connected with the first capacitor electrode through the fourth contact hole and having a different area from the first capacitor electrode on the second region on the interlayer insulating layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification
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Current AssigneeSamsung Display Company Limited (Samsung Electronics Co. Ltd.)
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Original AssigneeSamsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
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InventorsKim, Jong-Yun
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current257/40
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CPC Class CodesH01L 27/1255 integrated with passive dev...H01L 28/40 CapacitorsH10K 59/1216 the pixel elements being ca...H10K 59/131 Interconnections, e.g. wiri...
