THREE DIMENSIONAL NAND MEMORY

• US 20080237602A1
• Filed: 03/27/2007
• Published: 10/02/2008
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: MOKHLESI, Nima, SCHEUERLEIN, Roy
• Granted Patent: US 7,851,851 B2
• Time in Patent Office: Days
• US Class Current: 257/67
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

Claims

1. A monolithic, three dimensional NAND string comprising at least a first memory cell located over a second memory cell, wherein a semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

2. The NAND string of claim 1, wherein:

the NAND string is formed vertically over a substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located over the substrate and below the first device level.

3. The NAND string of claim 1, further comprising a select transistor located below the second memory cell.

4. The NAND string of claim 3, wherein:

the select transistor is located on a substrate or in a trench in the substrate; and

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor.

5. The NAND string of claim 4, wherein:

the semiconductor active region of the select transistor comprises a pillar having a square or rectangular cross section when viewed from above; and

the semiconductor active region of the second memory cell comprises a pillar having a square or rectangular cross section when viewed from above, which is not aligned with the semiconductor active region of the select transistor and which extends laterally past the semiconductor active region of the select transistor.

6. The NAND string of claim 1, wherein:

the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar; and

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar.

7. The NAND string of claim 6, further comprising:

a first charge storage dielectric located adjacent to the first conductivity type semiconductor region in the first pillar;

a first control gate located adjacent to the first charge storage dielectric;

a second charge storage dielectric located adjacent to the first conductivity type semiconductor region in the second pillar; and

a second control gate located adjacent to the second charge storage dielectric.

8. A monolithic, three dimensional NAND string comprising at least a first memory cell located over a second memory cell, wherein a semiconductor active region of at least the first memory cell comprises recrystallized polysilicon.

9. The NAND string of claim 8, wherein:

the NAND string is formed vertically over a substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located over the substrate and below the first device level.

10. The NAND string of claim 8, further comprising wiring and a select transistor located below the second memory cell.

11. The NAND string of claim 10, wherein:

the select transistor is located on a substrate or in a trench in the substrate; and

a semiconductor active region of the second memory cell comprises recrystallized polysilicon.

12. The NAND string of claim 11, wherein:

the semiconductor active region of the select transistor comprises a pillar having a square or rectangular cross section when viewed from above; and

the semiconductor active region of the second memory cell comprises a pillar having a square or rectangular cross section when viewed from above, which is not aligned with the semiconductor active region of the select transistor and which extends laterally past the semiconductor active region of the select transistor.

13. The NAND string of claim 8, wherein:

the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

a semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar; and

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar.

14. The NAND string of claim 13, further comprising:

a first charge storage dielectric located adjacent to the first conductivity type semiconductor region in the first pillar;

a first control gate located adjacent to the first charge storage dielectric;

a second charge storage dielectric located adjacent to the first conductivity type semiconductor region in the second pillar; and

a second control gate located adjacent to the second charge storage dielectric.

15. A monolithic, three dimensional NAND string comprising at least a first memory cell located over a second memory cell, wherein at least one region of the NAND string is planarized.

16. The NAND string of claim 15, wherein:

the NAND string is formed vertically over a substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located over the substrate and below the first device level.

17. The NAND string of claim 15, further comprising a select transistor located below the second memory cell.

18. The NAND string of claim 17, wherein:

the select transistor is located on a substrate or in a trench in the substrate;

the semiconductor active region of the select transistor comprises a pillar having a square or rectangular cross section when viewed from above; and

the semiconductor active region of the second memory cell comprises a pillar having a square or rectangular cross section when viewed from above, which is not aligned with the semiconductor active region of the select transistor and which extends laterally past the semiconductor active region of the select transistor.

19. The NAND string of claim 15, wherein:

a semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

a semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar;

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar; and

the first pillar comprises recrystallized polysilicon or epitaxially grown silicon on the second pillar.

20. The NAND string of claim 19, further comprising:

a first charge storage dielectric located adjacent to the first conductivity type semiconductor region in the first pillar;

a first control gate located adjacent to the first charge storage dielectric;

a second charge storage dielectric located adjacent to the first conductivity type semiconductor region in the second pillar; and

a second control gate located adjacent to the second charge storage dielectric.

21. The NAND string of claim 15, wherein the at least one region of the NAND string which is planarized comprises a semiconductor active region of the first memory cell.

22. The NAND string of claim 21, wherein the at least one region of the NAND string which is planarized further comprises a control gate of the first memory cell.

23. The NAND string of claim 22, wherein the at least one region of the NAND string which is planarized further comprises:

a semiconductor active region of the second memory cell;

a control gate of the second memory cell; and

an insulating layer which insulates the NAND string from at least one other adjacent NAND string.

24. A monolithic, three dimensional NAND device, comprising at least a first NAND device level located over a second NAND device level, wherein a semiconductor layer of the first NAND device level is formed epitaxially over a semiconductor layer of the second NAND device level, such that a defined boundary exists between the semiconductor layer of the first NAND device level and the semiconductor layer of the second NAND device level.

25. The device of claim 24, wherein:

the semiconductor layer the first NAND device level comprises a single crystal silicon active region; and

the semiconductor layer the second NAND device level comprises a single crystal silicon active region.