Flash memory device

• US 20080237687A1
• Filed: 09/07/2007
• Published: 10/02/2008
• Est. Priority Date: 03/29/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Song, I-hun, Park, Young-soo, Jin, Young-gu, Kang, Dong-hun, Kim, Chang-jung, Park, Jae-chul
• Application Number:
  US11/898,037
• Publication Number:
  US 20080237687A1
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Provided is a flash memory device including a gate structure on a substrate. The flash memory device includes a charge supply layer including a ZnO based material formed between a substrate and a gate structure or formed on the gate structure. Accordingly, the flash memory device can be formed to be of a bottom gate type or of a top gate type by including the charge supply layer. Also, the flash memory device may be realized to be any of a charge trap type and a floating gate type.

Claims

1. A flash memory device comprising a gate structure on a substrate, the flash memory device comprising:

a charge supply layer including a ZnO based material formed between the substrate and the gate structure or formed on the gate structure.

2. The flash memory device of claim 1, wherein the charge supply layer is formed of a material including ZnO or GaInZnO.

3. The flash memory device of claim 1, wherein the charge supply layer is formed of a material including a(In₂O₃).b(Ga₂O₃).c(ZnO) (where, a, b, and c are real numbers satisfying the condition:

a≧

O, b≧

O, c>

0).

4. The flash memory device of claim 3, wherein the charge supply layer is formed of a material including a(In₂O₃).b(Ga₂O₃).c(ZnO) (where a, b, and c are real numbers satisfying the condition:

a≧

1, b≧

1, 0<

c≦

1).

5. The flash memory device of claim 1, further comprising a buffer layer between the substrate and the charge supply layer.

6. The flash memory device of claim 5, wherein the buffer layer is formed to include one selected from the group consisting of a p-type semiconductor material, an intrinsic semiconductor, NiO, CuAlO₂, SrCu₂O₂, LaCuOS, SiO₂, and SiN_x.

7. The flash memory device of claim 5, further comprising a source/drain region formed in the charge supply layer to be connected to the gate structure.

8. The flash memory device of claim 7, wherein the source/drain region is formed by plasma processing.

9. The flash memory device of claim 1, further comprising a source/drain region formed in the charge supply layer to be connected to the gate structure.

10. The flash memory device of claim 9, wherein the source/drain region is formed by plasma processing.

11. The flash memory device of claim 1, wherein the flash memory device is of a top-gate type in which the gate structure is formed on the charge supply layer, and

the gate structure includes a tunneling insulating layer, a charge trap layer, a blocking insulating layer, and a control gate layer sequentially stacked on the charge supply layer.

12. The flash memory device of claim 1, wherein the flash memory device is of a top-gate type in which the gate structure is formed on the charge supply layer, and

the gate structure includes a tunneling insulating layer, a floating gate layer, an insulating layer between gates, and a control gate layer sequentially stacked on the charge supply layer.

13. The flash memory device of claim 1, wherein the flash memory device is of a bottom gate type in which the gate structure is formed on the substrate and the charge supply layer is formed on the gate structure,

wherein the gate structure includes a control gate layer, a blocking insulating layer, a charge trap layer, and a tunneling insulating layer sequentially stacked on the substrate, and

the charge supply layer is formed on the tunneling insulating layer.

14. The flash memory device of claim 1, wherein the flash memory device is of a bottom gate type in which the gate structure is formed on the substrate and the charge supply layer is formed on the gate structure,

wherein the gate structure includes a control gate layer, a blocking insulating layer, a floating gate layer, and a tunneling insulating layer sequentially stacked on the substrate, and

the charge supply layer is formed on the tunneling insulating layer.