PATTERNED BACKSIDE STRESS ENGINEERING FOR TRANSISTOR PERFORMANCE OPTIMIZATION

• US 20080237729A1
• Filed: 04/03/2008
• Published: 10/02/2008
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Gilroy J. Vandentop, Rajashree Baskaran
• Original Assignee: Gilroy J. Vandentop, Rajashree Baskaran
• Inventors: Baskaran, Rajashree, Vandentop, Gilroy J.
• Granted Patent: US 7,821,073 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054

Abstract

Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.

Claims

1. An apparatus comprising:

a substrate surface having a first transistor type region and a second transistor type region; and

a backside stress region on a substrate surface opposite the first transistor type region.

2. The apparatus of claim 1, wherein the back side stress region comprises at least one of an atomic implant or a thin film.

3. The apparatus of claim 1, wherein the first transistor type region comprises a PMOS transistor, the second transistor type region comprises a NMOS transistor, and the back side stress region comprises a Germanium implant.

4. The apparatus of claim 1, wherein the first transistor type region comprises a NMOS transistor, the second transistor type region comprises a PMOS transistor, and the back side stress region comprises a nitride thin film.

5. The apparatus of claim 1, further comprising:

a second backside stress region on a substrate surface opposite the second transistor type region.

6. The apparatus of claim 5, wherein the first transistor type region comprises a NMOS transistor, the second transistor type region comprises a PMOS transistor, the back side stress region comprises a nitride thin film, and the second backside stress engineering region comprises a Germanium implant.

7. The apparatus of claim 5, further comprising:

a third transistor type region on the substrate surface; and

a third backside stress region on a substrate surface opposite the third transistor type region.

8. An apparatus comprising:

a front surface of a thinned wafer mounted to a wafer support system;

a pattern on a back surface of the thinned wafer; and

a backside stress region on the back surface of the thinned wafer.

9. The apparatus of claim 8, wherein the wafer support system comprises glass.

10. The apparatus of claim 8, wherein the back side stress region comprises at least one of an atomic implant or a thin film.

11. An apparatus comprising:

a first surface of a substrate having a PMOS transistor region and a NMOS transistor region;

a first backside stress region comprising an atomic implant on a substrate surface opposite the PMOS transistor region; and

a second backside stress region comprising a thin film layer on the substrate surface opposite the NMOS transistor region.

12. The apparatus of claim 11, wherein the atomic implant includes a Germanium implant.

13. The apparatus of claim 11, wherein the thin film layer includes a nitride layer.

14. An apparatus comprising:

a first surface of a substrate having a first transistor type region and a second transistor type region; and

a heat spreader attached to a substrate surface opposite the first surface, the heat spreader having a portion opposite the first transistor type region that is thinner than a portion opposite the second transistor type region.

15. The apparatus of claim 14, wherein the first transistor type region comprises a NMOS transistor and the second transistor type region comprises a PMOS transistor.

16. The apparatus of claim 14, wherein the portion opposite the first transistor type region is about 0.1 to 1.25 mm thick and the portion opposite the second transistor type region is about 1.25 to 2.75 mm thick.

17. The apparatus of claim 14, wherein the portion opposite the first transistor type region is about 0.25 to 1.1 mm thick and the portion opposite the second transistor type region is about 1.25 to 2.75 mm thick.

18. The apparatus of claim 14, wherein the portion opposite the first transistor type region is about 0.5 to 1.0 mm thick and the portion opposite the second transistor type region is about 1.5 to 2.5 mm thick.

19. The apparatus of claim 14, further comprising:

a thermal interface material between the substrate surface opposite the first surface and the heat spreader.

20. The apparatus of claim 19, wherein the heat spreader includes copper and the thermal interface material includes gold-tin.

21. A method comprising:

forming a pattern over a first surface of a substrate, the substrate having a first transistor type region and a second transistor type region on a second surface, the pattern covering at least a portion of the first surface opposite the second transistor type region and exposing at least a portion of the first surface opposite the first transistor type region; and

inducing a back side stress in the at least one first transistor type region.

22. The method of claim 21, wherein inducing the back side stress includes implanting atoms into the first surface.

23. The method of claim 21, wherein inducing the back side stress includes providing a thin film.

24. The method of claim 21, wherein the first transistor type region comprises a PMOS transistor and the second transistor type region comprises a NMOS transistor.

25. The method of claim 24, wherein inducing the back side stress includes implanting Germanium.

26. The method of claim 21, wherein the first transistor type region comprises a NMOS transistor and the second transistor type region comprises a PMOS transistor.

27. The method of claim 26, wherein inducing the back side stress includes providing a nitride layer.

28. The method of claim 21, further comprising:

forming a second pattern over the first surface, wherein the second pattern covers at least a portion of the first surface opposite the first transistor type region and exposes at least a portion of the first surface opposite the second transistor type region; and

inducing a second back side stress in the at least one second transistor type region using the second.

29. The method of claim 28, wherein inducing the back side stress includes copper plating at a first temperature and inducing the second backside stress includes copper plating at a second temperature.

30. The method of claim 21, further comprising:

mounting the second surface of the substrate to a wafer support system;

thinning the substrate; and

depositing a diffusion barrier on the first surface of the substrate.

31. The method of claim 21, further comprising:

providing front side stress engineering to the second transistor type region.

32. The method of claim 21, wherein forming the pattern includes a photo-patterning process.

33. A method comprising:

selectively inducing stress to the back side of a first transistor type region of a substrate having the first transistor type region and a second transistor type region.

34. The method of claim 33, wherein selectively inducing stress comprises at least one of implanting atoms or providing a thin film.

35. The method of claim 33, further comprising:

selectively inducing a second stress to the backside of the at least one second transistor type region.

36. The method of claim 33, wherein the first transistor type region comprises a PMOS transistor and inducing stress includes implanting Germanium atoms.

37. The method of claim 33, wherein the first transistor type region comprises a NMOS transistor and inducing stress includes providing a nitride layer.