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PATTERNED BACKSIDE STRESS ENGINEERING FOR TRANSISTOR PERFORMANCE OPTIMIZATION

  • US 20080237729A1
  • Filed: 04/03/2008
  • Published: 10/02/2008
  • Est. Priority Date: 09/24/2004
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a substrate surface having a first transistor type region and a second transistor type region; and

    a backside stress region on a substrate surface opposite the first transistor type region.

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