METHOD FOR PRESERVING PROCESSING HISTORY ON A WAFER

• US 20080237811A1
• Filed: 03/30/2007
• Published: 10/02/2008
• Est. Priority Date: 03/30/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Pal, Rohit, Brown, David F.
• Application Number:
  US11/694,057
• Publication Number:
  US 20080237811A1
• Time in Patent Office: Days
• US Class Current: 257/632
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature.

Claims

1. A method for capturing process history, comprising:

performing at least a first process for forming features on a semiconducting substrate;

forming a first cap over a first region of the semiconducting substrate after performing the first process;

performing at least a second process for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process;

measuring a first characteristic of a first feature in the first region; and

measuring a second characteristic of a second feature in the second region.

2. The method of claim 1, further comprising:

forming a second cap over at least a portion of the second region after performing the second process;

performing at least a third process for forming the features, the third process affecting the features in a third region other than the portions of the first and second regions covered by the first and second caps; and

measuring a third characteristic of a third feature in the third region.

3. The method of claim 1, further comprising determining at least one recipe parameter for the first process or the second process based on the first and second measured characteristics.

4. The method of claim 2, further comprising determining at least one recipe parameter for the first process, the second process, or the third process based on at least one of the first, second, or third measured characteristics.

5. The method of claim 1, wherein the first process comprises forming a material, the second process comprises a material removal process, and the method further comprises comparing the first and second measured characteristics to determine a material loss due to the second process.

6. The method of claim 5, wherein the material comprises a stressed material, and the first process comprises forming the stressed material in a recess defined in a semiconductor layer.

7. The method of claim 1, wherein the first cap covers a portion of a die region defined on the semiconducting substrate.

8. The method of claim 1, wherein the first cap covers an entire die region defined on the semiconducting substrate.

9. The method of claim 1, wherein the first cap covers a test structure disposed between die regions defined on the semiconducting substrate.

10. A method, comprising:

processing a semiconducting substrate in a process flow;

forming a first cap over a first region of the semiconducting substrate at a first point in the process flow;

forming a second cap over a second region of the semiconducting substrate at a second point in the process flow;

cross-sectioning the semiconducting substrate across at least the first region and the second region;

measuring a first characteristic of the semiconducting substrate in the first region; and

measuring a second characteristic of the semiconducting substrate in the second region.

11. The method of claim 10, wherein the first and second caps are disposed above a first layer.

12. The method of claim 10, wherein the first cap is disposed above a first layer and below a second layer, and the second cap is disposed above the second layer.

13. The method of claim 12, wherein the first layer comprises a device layer, and the second layer comprises a metallization layer.

14. The method of claim 10, wherein the first cap covers a portion of a die region.

15. The method of claim 10, wherein the first cap covers an entire die region.

16. The method of claim 10, wherein the first cap covers a test structure disposed between die regions.

17. The method of claim 10, further comprising determining at least one recipe parameter for processing subsequent semiconducting substrates based on the first and second measured characteristics.

18. The method of claim 10, wherein the first and second characteristics comprise material thickness characteristics.

19. The method of claim 10, wherein the first and second characteristics comprise spacer width characteristics.

20. The method of claim 10, wherein the first and second characteristics comprise recess depth characteristics.

21. The method of claim 10, wherein the first and second characteristics comprise dopant profile characteristics.

22. A wafer, comprising:

a first partially completed feature disposed in a first region of the wafer;

a first cap formed above the first partially completed feature; and

a second partially completed feature disposed in a second region of the wafer different than the first region, the second partially completed feature being at a later stage of completion than the first partially completed feature.

23. The wafer of claim 22, comprising a second cap formed above the second partially completed feature.

24. The wafer of claim 23, further comprising a third feature disposed in a third region of the wafer different than the first and second regions, the third feature being at a later stage of completion than the second partially completed feature.