Ball grid array package and its substrate

• US 20080237855A1
• Filed: 03/28/2007
• Published: 10/02/2008
• Est. Priority Date: 03/28/2007
• Status: Abandoned Application

• Current Assignee: Powertech Technology Inc
• Original Assignee: Powertech Technology Inc
• Inventors: Fan, Wen-Jeng, Yu, Tsai-Chuan
• Application Number:
  US11/727,902
• Publication Number:
  US 20080237855A1
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities.

Claims

1. A BGA package comprising:

a substrate having a top surface, a bottom surface, a plurality of ball pads formed on the bottom surface and at least a core layer between the top surface and the bottom surface;

a chip disposed on the top surface of the substrate and electrically connected to the substrate; and

a plurality of solder balls disposed on the ball pads;

wherein the core layer has a plurality of corner cavities filled with low-modulus materials, and some of the ball pads at the corners of the substrate are disposed under the corner cavities.

2. The BGA package of claim 1, wherein the corner cavities are rectangular.

3. The BGA package of claim 1, wherein the chip is attached to a die-attaching area on the top surface of the substrate, the die-attaching area having a plurality of corners overlapped on the corner cavities.

4. The BGA package of claim 1, wherein the low-modulus materials are embedded between the top surface and the bottom surface of the substrate.

5. The BGA package of claim 3, wherein the low-modulus materials are exposed on the top surface and contacted the corners of the chip.

6. The BGA package of claim 1, further comprising a plurality of bonding wires electrically connecting the chip to the substrate.

7. The BGA package of claim 6, further comprising an encapsulant encapsulating at least a portion of the chip and the bonding wires.

8. A substrate for BGA packages, having a top surface and a bottom surface and comprising:

at least a core layer between the top surface and the bottom surface; and

a plurality of ball pads formed on the bottom surface;

wherein the core layer has a plurality of corner cavities filled with low-modulus materials, and some of the ball pads at the corners of the substrate are disposed under the corner cavities.

9. The substrate of claim 8, wherein the corner cavities are rectangular.

10. The substrate of claim 8, wherein the top surface of the substrate includes a die-attaching area having a plurality of corners overlapped on the corner cavities.

11. The substrate of claim 8, wherein the low-modulus materials are embedded between the top surface and the bottom surface of the substrate.

12. The substrate of claim 8, wherein the low-modulus materials are exposed on the top surface for contacting a plurality of corners of a chip.

13. A BGA package comprising:

a substrate having a top surface, a bottom surface, a plurality of ball pads formed on the bottom surface, and at least a core layer between the top surface and the bottom surface;

a chip disposed on the top surface of the substrate and electrically connected to the substrate;

a plurality of solder balls disposed on the ball pads; and

a stress buffer patterned and embedded in the core layer;

wherein at least one of the ball pads bearing the most concentrated stress is disposed under the stress buffer.

14. The BGA package of claim 13, wherein the stress buffer is an elastic rectangular block.

15. The BGA package of claim 13, wherein the chip is attached to a die-attaching area on the top surface of the substrate, the die-attaching area having a plurality of corners overlapped on the stress buffer.

16. The BGA package of claim 13, further comprising a plurality of bonding wires electrically connecting the chip to the substrate.

17. The BGA package of claim 16, further comprising an encapsulant encapsulating at least a portion of the chip and the bonding wires.

18. A substrate for BGA packages, having a top surface and a bottom surface and comprising:

at least a core layer between the top surface and the bottom surface; and

a plurality of ball pads formed on the bottom surface; and

a stress buffer patterned and embedded in the core layer;

wherein at least one of the ball pads bearing the most concentrated stress is disposed under the stress buffer.

19. The substrate of claim 18, wherein the stress buffer is an elastic rectangular block.

20. The substrate of claim 18, wherein the top surface of the substrate includes a die-attaching area having a plurality of corners overlapped on the stress buffer.