Implementation of diffusion barrier in 3D memory

• US 20080237862A1
• Filed: 03/30/2007
• Published: 10/02/2008
• Est. Priority Date: 03/30/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Tanaka, Yoichiro
• Granted Patent: US 8,124,971 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.

Claims

1. A memory cell, comprising:

a first conductor in a trench in a first dielectric;

a second conductor in a trench in a second dielectric; and

a pillar coupling the first and second conductors, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell,

at least one of the first and second conductors partially recessed in the first and second dielectrics, respectively, the at least one of a partial recess of the first conductor and a partial recess of the second conductor filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier.

2. The cell of claim 1, the pillar comprising:

a semiconductor over the first conductor; and

an antifuse over the semiconductor, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell.

3. The cell of claim 2, the pillar comprising:

a hardmask over the antifuse.

4. The cell of claim 3, the conductors comprising copper.

5. The cell of claim 4, at least one of the trenches lined with the first diffusion barrier such that at least one of the first and second conductors are surrounded by the first diffusion barrier.

6. The cell of claim 5, the pillar comprising:

a second diffusion barrier between the antifuse and the hardmask.

7. The cell of claim 6, comprising:

a third diffusion barrier over the first diffusion barrier in the at least one recess.

8. The cell of claim 7, at least one of the trenches lined with the third diffusion barrier such that at least one of the first and second conductors are surrounded by the first diffusion barrier with the first diffusion barrier surrounded by the third diffusion barrier.

9. The cell of claim 8, the pillar not comprising germanium or a germanium alloy.

10. A memory cell, comprising:

a first conductor;

a second conductor; and

a pillar coupling the first and second conductors, the pillar not comprising germanium or a germanium alloy, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell, at least one of;

the first conductor in a trench in a first dielectric, and

the second conductor in a trench in a second dielectric.

12. The cell of claim 10, at least one of the first and second conductors partially recessed in the first and second dielectrics, respectively, at least one of a partial recess of the first conductor and a partial recess of the second conductor filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier.

13. The cell of claim 12, the pillar comprising:

a semiconductor over the first conductor; and

an antifuse over the semiconductor, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell.

14. The cell of claim 13, the pillar comprising:

a hardmask over the antifuse.

15. The cell of claim 14, the conductors comprising copper.

16. The cell of claim 15, at least one of the trenches lined with the first diffusion barrier such that at least one of the first and second conductors are surrounded by the first diffusion barrier.

17. The cell of claim 16, the pillar comprising:

a second diffusion barrier between the antifuse and the hardmask.

18. The cell of claim 17, comprising:

a third diffusion barrier over the first diffusion barrier in the at least one recess.

19. The cell of claim 18, at least one of the trenches lined with the third diffusion barrier such that at least one of the first and second conductors are surrounded by the first diffusion barrier with the first diffusion barrier surrounded by the third diffusion barrier.

11. (canceled)

20. A memory cell, comprising:

a first copper conductor;

a pillar over the first conductor; and

a second copper conductor over the pillar, the pillar comprising;

a semiconductor over the first conductor;

an antifuse over the semiconductor; and

a hardmask over the antifuse, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell.

21. The cell of claim 20, at least one of:

the first conductor in a trench in a first dielectric, and

the second conductor in a trench in a second dielectric.

22. The cell of claim 21, at least one of the first and second conductors partially recessed in the first and second dielectrics, respectively, at least one of a partial recess of the first conductor and a partial recess of the second conductor filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier.

23. The cell of claim 22, at least one of the trenches lined with the first diffusion barrier such that at least one of the first and second conductors are surrounded by the first diffusion barrier.

24. The cell of claim 23, the pillar comprising:

a second diffusion barrier between the antifuse and the hardmask.

25. The cell of claim 24, comprising:

a third diffusion barrier over the first diffusion barrier in the at least one recess.

26. The cell of claim 25, at least one of the trenches lined with the third diffusion barrier such that at least one of the first and second conductors are surrounded by the first diffusion barrier with the first diffusion barrier surrounded by the third diffusion barrier.

27. The cell of claim 26, the semiconductor not comprising germanium or a germanium alloy.