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Implementation of diffusion barrier in 3D memory

  • US 20080237862A1
  • Filed: 03/30/2007
  • Published: 10/02/2008
  • Est. Priority Date: 03/30/2007
  • Status: Active Grant
First Claim
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1. A memory cell, comprising:

  • a first conductor in a trench in a first dielectric;

    a second conductor in a trench in a second dielectric; and

    a pillar coupling the first and second conductors, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell,at least one of the first and second conductors partially recessed in the first and second dielectrics, respectively, the at least one of a partial recess of the first conductor and a partial recess of the second conductor filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier.

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