Implementation of diffusion barrier in 3D memory
First Claim
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1. A memory cell, comprising:
- a first conductor in a trench in a first dielectric;
a second conductor in a trench in a second dielectric; and
a pillar coupling the first and second conductors, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell,at least one of the first and second conductors partially recessed in the first and second dielectrics, respectively, the at least one of a partial recess of the first conductor and a partial recess of the second conductor filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier.
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Abstract
One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.
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Citations
27 Claims
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1. A memory cell, comprising:
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a first conductor in a trench in a first dielectric; a second conductor in a trench in a second dielectric; and a pillar coupling the first and second conductors, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell, at least one of the first and second conductors partially recessed in the first and second dielectrics, respectively, the at least one of a partial recess of the first conductor and a partial recess of the second conductor filled with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory cell, comprising:
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a first conductor; a second conductor; and a pillar coupling the first and second conductors, the pillar not comprising germanium or a germanium alloy, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell, at least one of; the first conductor in a trench in a first dielectric, and the second conductor in a trench in a second dielectric. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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11. (canceled)
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20. A memory cell, comprising:
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a first copper conductor; a pillar over the first conductor; and a second copper conductor over the pillar, the pillar comprising; a semiconductor over the first conductor; an antifuse over the semiconductor; and a hardmask over the antifuse, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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Specification