SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20080237875A1
• Filed: 03/12/2008
• Published: 10/02/2008
• Est. Priority Date: 03/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, SUZAWA, Hideomi, SASAGAWA, Shinya, KURATA, Motomu
• Granted Patent: US 7,763,981 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.

Claims

1. A semiconductor device comprising:

a semiconductor layer formed over an insulating surface;

a first insulating layer formed over the semiconductor layer;

a gate electrode formed over the first insulating layer;

a second insulating layer formed over the gate electrode; and

a conductive layer formed over the second insulating layer,

wherein the conductive layer is connected to the semiconductor layer via a first opening and second opening,

wherein the first opening is formed at least in the second insulating layer,

wherein the first opening reaches the semiconductor layer,

wherein the second opening is formed at least in the semiconductor layer,

wherein the second opening reaches the insulating surface, and

wherein a top-view area of the second opening is smaller than that of the first opening.

2. The semiconductor device according to claim 1,

wherein an insulator is provided at a side surface of the semiconductor layer.

3. The semiconductor device according to claim 1,

wherein the semiconductor layer comprise a silicide region.

4. The semiconductor device according to claim 1,

wherein a thickness of the semiconductor layer is 10 to 30 nm.

5. The semiconductor device according to claim 1,

wherein the first opening is further formed in the first insulating layer.

6. A semiconductor device comprising:

a first insulating layer formed over a substrate;

a second insulating layer having an insulating surface, formed over the first insulating layer;

a semiconductor layer formed over the insulating surface;

a third insulating layer formed over the semiconductor layer;

a gate electrode formed over the third insulating layer;

a fourth insulating layer formed over the gate electrode; and

a conductive layer formed over the fourth insulating layer,

wherein the conductive layer is connected to the semiconductor layer via a first opening and second opening,

wherein the first opening is formed at least in the fourth insulating layer,

wherein the first opening reaches the semiconductor layer,

wherein the second opening is formed at least in the semiconductor layer and the second insulating layer,

wherein the second opening reaches the first insulating layer, and

wherein a top-view area of the second opening is smaller than that of the first opening.

7. The semiconductor device according to claim 6,

wherein an insulator is provided at a side surface of the semiconductor layer.

8. The semiconductor device according to claim 6,

wherein the semiconductor layer comprise a silicide region.

9. The semiconductor device according to claim 6,

wherein a thickness of the semiconductor layer is 10 to 30 nm.

10. The semiconductor device according to claim 6,

wherein the first opening is further formed in the third insulating layer.

11. A method for manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer over an insulating surface;

forming a first insulating layer over the semiconductor layer;

forming a gate electrode over the first insulating layer;

forming a second insulating layer over the gate electrode;

forming a first opening at least in the second insulating layer, wherein the first opening reaches the semiconductor layer;

forming a second opening at least in the semiconductor layer, wherein the second opening reaches the insulating surface; and

forming a conductive layer over the second insulating layer,

wherein the conductive layer is connected to the semiconductor layer via the first opening and the second, and

wherein a top-view area of the second opening is smaller than that of the first opening.

12. The method for manufacturing a semiconductor device according to claim 11,

wherein an insulator is provided at a side surface of the semiconductor layer.

13. The method for manufacturing a semiconductor device according to claim 11,

wherein the semiconductor layer comprise a silicide region.

14. The method for manufacturing a semiconductor device according to claim 11,

wherein a thickness of the semiconductor layer is 10 to 30 nm.

15. The method for manufacturing a semiconductor device according to claim 11,

wherein the first opening is further formed in the first insulating layer.

16. A method for manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer over an insulating surface;

forming a first insulating layer over the semiconductor layer;

forming a gate electrode over the first insulating layer;

forming a second insulating layer over the gate electrode;

forming a resist mask over the second insulating layer;

forming a first opening at least in the second insulating layer, wherein the first opening reaches the semiconductor layer;

forming a second opening at least in the semiconductor layer, wherein the second opening reaches the insulating surface; and

forming a conductive layer over the second insulating layer,

wherein the conductive layer is connected to the semiconductor layer via the first opening and the second opening,

wherein the first opening is formed by wet etching using the resist mask,

wherein the second opening is formed by dry etching using the resist mask, and

wherein a top-view area of the second opening is smaller than that of the first opening.

17. The method for manufacturing a semiconductor device according to claim 16,

wherein an insulator is provided at a side surface of the semiconductor layer.

18. The method for manufacturing a semiconductor device according to claim 16,

wherein the semiconductor layer comprise a silicide region.

19. The method for manufacturing a semiconductor device according to claim 16,

wherein a thickness of the semiconductor layer is 10 to 30 nm.

20. The method for manufacturing a semiconductor device according to claim 16,

wherein the first opening is further formed in the first insulating layer.

21. A method for manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer over an insulating surface;

forming a first insulating layer over the semiconductor layer;

forming a gate electrode over the first insulating layer;

forming a second insulating layer over the gate electrode;

forming a first resist mask over the second insulating layer;

forming a first opening at least in the second insulating layer, wherein the first opening reaches the semiconductor layer;

forming a second resist mask by etching the first resist mask;

forming a second opening at least in the semiconductor layer, wherein the second opening reaches the insulating surface; and

forming a conductive layer over the second insulating layer,

wherein the conductive layer is connected to the semiconductor layer via the first opening and the second opening,

wherein the first opening is formed by etching using the first resist mask,

wherein the second opening is formed by etching using the second resist mask, and

wherein a top-view area of the second opening is smaller than that of the first opening.

22. The method for manufacturing the semiconductor device, according to claim 21,

wherein the first opening and the second opening are formed by dry etching.

23. The method for manufacturing a semiconductor device according to claim 21,

wherein an insulator is provided at a side surface of the semiconductor layer.

24. The method for manufacturing a semiconductor device according to claim 21,

wherein the semiconductor layer comprise a silicide region.

25. The method for manufacturing a semiconductor device according to claim 21,

wherein a thickness of the semiconductor layer is 10 to 30 nm.

26. The method for manufacturing a semiconductor device according to claim 21,

wherein the first opening is further formed in the first insulating layer.