SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20080237876A1
• Filed: 03/12/2008
• Published: 10/02/2008
• Est. Priority Date: 03/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SASAGAWA, Shinya
• Granted Patent: US 7,709,368 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.

Claims

1. A semiconductor device comprising:

a semiconductor layer formed over a substrate;

a first insulating layer formed over the semiconductor layer;

a gate electrode formed over the first insulating layer;

a second insulating layer formed over the gate electrode;

an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer;

a step portion formed at a side surface of the second insulating layer in the opening; and

a conductive layer which is formed over the second insulating layer, covers a side surface of the opening, and is in contact with the semiconductor layer.

3. The semiconductor device according to claim 1, further comprising an insulating sidewall formed at a side surface of the semiconductor layer.

2. A semiconductor device comprising:

a semiconductor layer formed over a substrate;

a first insulating layer formed over the semiconductor layer;

a gate electrode formed over the first insulating layer;

a second insulating layer formed over the gate electrode;

an opening which reaches the semiconductor layer and is formed at least in the second insulating layer;

a step portion formed at a side surface of the second insulating layer in the opening; and

a conductive layer which is formed over the second insulating layer, covers a side surface of the opening, and is in contact with the semiconductor layer,

wherein a silicide layer is formed on at least a portion exposed by the opening of the semiconductor layer.

4. The semiconductor device according to claim 2, further comprising an insulating sidewall formed at a side surface of the semiconductor layer.

5. The semiconductor device according to claim 2, further comprising an insulating sidewall formed at a side surface of the gate electrode.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer over a substrate;

forming a first insulating layer over the semiconductor layer;

forming a gate electrode over the first insulating layer;

forming a second insulating layer over the gate electrode;

forming a resist having a step portion at a side surface over the second insulating layer;

forming an opening which reaches the semiconductor layer at least in the second insulating layer so as to have a step portion at a side surface of the second insulating layer by etching using the resist as a mask; and

forming a conductive layer to be in contact with the semiconductor layer at a side surface of the opening and over the second insulating layer.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the opening is formed by dry etching.

9. The method for manufacturing a semiconductor device according to claim 6, wherein an insulating sidewall is formed at a side surface of the semiconductor layer.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating layer over a substrate;

forming a second insulating layer over the first insulating layer;

forming a semiconductor layer over the second insulating layer;

forming a third insulating layer over the semiconductor layer;

forming a gate electrode over the third insulating layer;

forming a fourth insulating layer over the gate electrode;

forming a resist having a step portion at a side surface over the fourth insulating layer;

forming an opening which reaches the first insulating layer at least in the second insulating layer, the semiconductor layer, and the fourth insulating layer by etching using the resist as a mask such that the opening formed in the semiconductor layer is smaller than that formed in the fourth insulating layer; and

forming a conductive layer to be in contact with the first insulating layer at a side surface of the opening and over the fourth insulating layer.

10. The method for manufacturing a semiconductor device according to claim 7, wherein the opening is formed by dry etching.

11. The method for manufacturing a semiconductor device according to claim 7, wherein an insulating sidewall is formed at a side surface of the semiconductor layer.