Semiconductor Device and Wiring Board

• US 20080237890A1
• Filed: 05/18/2005
• Published: 10/02/2008
• Est. Priority Date: 05/21/2004
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: ET US Holdings LLC (Forvia SE)
• Inventors: Tago, Masamoto
• Granted Patent: US 7,692,287 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 25/162 the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 Multilayer substrate
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A wiring board (20A) includes a first wiring portion (10A) having a plurality of wiring layers (1) and external connecting bumps (5), and at least one second wiring portion (15A) having a plurality of contact plugs (14). The second wiring portion is integrated with the first wiring portion such that each terminal (14a) of the second wiring portion is in direct contact with one of the wiring layers of the first wiring portion. Hence, there is no risk to produce an internal stress caused by the diffused component of the solder bump in the junction portion between the second and first wiring portions. Accordingly, even when a semiconductor chip (30) of a low-k material is highly integrated on the wiring board, a highly reliable semiconductor device (50) can be obtained.

Claims

1. A semiconductor device characterized by comprising:

a wiring board comprising a plurality of connecting terminals arranged on one surface in a direction of thickness and a plurality of external connecting bumps arranged on the other surface in the direction of thickness; and

a semiconductor chip connected to said connecting terminals on said wiring board by flip chip bonding,

wherein said wiring board comprises;

a first wiring portion comprising a plurality of wiring layers and said external connecting bumps; and

at least one second wiring portion integrated with said first wiring portion on said first wiring portion,

said connecting terminals are made of contact plugs formed in through holes extending through said second wiring portion in the direction of thickness,

one end of said contact plug is in direct contact with one of said wiring layers,

a size of a surface of said second wiring portion on a side of said first wiring portion is smaller than a size of a surface of said first wiring portion on a side of said second wiring portion, and

a thermal expansion coefficient of said second wiring portion is smaller than a thermal expansion coefficient of said first wiring portion and equal to a thermal expansion coefficient of said semiconductor chip.

2. A semiconductor device according to claim 1, characterized in that said semiconductor chip is mounted on said second wiring portion, and

a size of a surface of said second wiring portion on which said semiconductor chip is mounted is larger than a size of a surface of said semiconductor chip which opposes the surface of said second wiring portion.

3. A semiconductor device according to claim 2, characterized in that when viewed from above, said second wiring portion is not less than 1 mm all around larger than said semiconductor chip.

4. A semiconductor device according to claim 1, characterized in that said semiconductor chip is mounted on said second wiring portion, and

a size of a surface of said second wiring portion on which said semiconductor chip is mounted is not more than a size of a surface of said semiconductor chip which opposes the surface of said second wiring portion.

5. A semiconductor device according to claim 1, characterized in that said second wiring portion is buried in said first wiring portion such that the other end of said contact plug is exposed.

6. A semiconductor device according to claim 1, characterized in that said semiconductor chip comprises at least one electrode terminal, and

said electrode terminal electrically connects to individual contact plugs.

7. A semiconductor device according to claim 1, characterized in that said semiconductor chip is a silicon chip,

said second wiring portion comprises a base made of one of silicon, ceramic, and photosensitive glass, and

said contact plugs are formed in said base.

8. A semiconductor device according to claim 1, characterized by further comprising at least one reinforcing frame member which is bonded on said wiring board.

9. A semiconductor device according to claim 8, characterized in that a thermal expansion coefficient of said reinforcing frame member is not more than a thermal expansion coefficient of said semiconductor chip.

10. A semiconductor device according to claim 8, characterized in that said reinforcing frame member partially covers said first wiring portion and at least one second wiring portion.

11. A semiconductor device according to claim 8, characterized by further comprising a heat sink which covers said reinforcing frame member, and is in contact with said semiconductor chip.

12. A semiconductor device according to claim 1, characterized by further comprising at least one functional element formed on at least one of a surface of said second wiring portion on a side of said first wiring portion, and a surface of said first wiring portion.

13. A wiring board characterized by comprising:

a first wiring portion comprising a plurality of wiring layers and a plurality of external connecting bumps; and

at least one second wiring portion comprising a plurality of connecting terminals configured to mount a semiconductor chip by flip chip bonding,

wherein said second wiring portion is integrated with said first wiring portion on said first wiring portion,

said connecting terminals are made of contact plugs formed in through holes extending through said second wiring portion in the direction of thickness,

one end of said contact plug is in direct contact with one of said wiring layers,

a size of a surface of said second wiring portion on a side of said first wiring portion is smaller than a size of a surface of said first wiring portion on a side of said second wiring portion, and

a thermal expansion coefficient of said second wiring portion is smaller than a thermal expansion coefficient of said first wiring portion and equal to a thermal expansion coefficient of said semiconductor chip.

14. A wiring board according to claim 13, characterized in that a size of a surface of said second wiring portion on which said semiconductor chip is mounted is larger than a size of a surface of said semiconductor chip which opposes the surface of said second wiring portion.

15. A wiring board according to claim 14, characterized in that when viewed from above, said second wiring portion is not less than 1 mm all around larger than said semiconductor chip mounted on said second wiring portion.

16. A wiring board according to claim 13, characterized in that a size of a surface of said second wiring portion on which said semiconductor chip is mounted is not more than a size of a surface of said semiconductor chip which opposes the surface of said second wiring portion.

17. A wiring board according to claim 13, characterized in that said second wiring portion is buried in said first wiring portion such that the other end of said contact plug is exposed.

18. A wiring board according to claim 13, characterized in that said semiconductor chip comprises at least one electrode terminal, and

the number of said connecting terminals of said second wring portion is equal to a total sum of said electrode terminals of said semiconductor chip to be mounted on said second wiring portion.

19. A wiring board according to claim 13, characterized in that said second wiring portion comprises a base made of one of silicon, ceramic, and photosensitive glass, and

said contact plugs are formed in said base.

20. A wiring board according to claim 13, characterized by further comprising at least one reinforcing frame member which is bonded on at least a periphery of said second portion on said first wiring portion.

21. A wiring board according to claim 20, characterized in that a thermal expansion coefficient of said reinforcing frame member is not more than a thermal expansion coefficient of said semiconductor chip.

22. A wiring board according to claim 20, characterized in that said reinforcing frame member partially covers said first wiring portion and at least one second wiring portion.

23. A wiring board according to claim 13, characterized by further comprising at least one functional element formed on at least one of a surface of said second wiring portion on a side of said first wiring portion, and a surface of said first wiring portion.