Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Random Access Memory

• US 20080238475A1
• Filed: 03/26/2008
• Published: 10/02/2008
• Est. Priority Date: 03/29/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kang, Seung H., Nowak, Matthew, Chua-Eoan, Lew
• Granted Patent: US 7,728,622 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/165 Auxiliary circuits
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.

Claims

1. A programmable logic array, comprising:

a plurality of spin transfer torque magnetic tunnel junction (MTJ) devices, arranged in an array; and

a plurality of programmable sources coupled to corresponding MTJ devices for changing the polarity of a free layer of each MTJ device;

wherein a first group of the MTJ devices are arranged into an input plane,

wherein a second group of the MTJ devices are arranged into an output plane, and

wherein the input plane and the output plane are combined to form a logic function based on the relative polarities of the free layer of each MTJ device.

2. The programmable logic array of claim 1, wherein each MTJ device contains a magnetic tunnel junction (MTJ) storage element that can be electrically programmed to a low resistance or high resistance state.

3. The programmable logic array of claim 2, wherein each row in the array is coupled to input columns via one of the plurality of MTJ devices.

4. The programmable logic array of claim 3, wherein a first input column is selected in a first row by setting a first MTJ coupling the first row to the first column to a low resistance state.

5. The programmable logic array of claim 4, wherein a second input column is not selected in a first row by setting a second MTJ coupling the first row to the second column to a high resistance state.

6. The programmable logic array of claim 4, wherein a first programmable source from the plurality of programmable sources is coupled to a column coupled to the first MTJ and a second programmable source from the plurality of programmable sources is coupled to a row coupled to the first MTJ.

7. The programmable logic array of claim 6, wherein the first programmable source and second programmable source are configured to provide a programming current for the first MTJ during a write operation.

8. The programmable logic array of claim 7, wherein the second programmable source is configured to provide a voltage sink during a read operation.

9. The programmable logic array of claim 1, wherein the input plane is a NOR plane and the output plane is a NOR plane.

10. The programmable logic array of claim 1, wherein the input plane is an AND plane and output plane is an OR plane.

11. The programmable logic array of claim 1, further comprising:

a MUX driver coupled between the input plane and output plane, wherein the MUX driver is configured to provide a read signal from a first row of the input plane to a MTJ of the output plane.

12. The programmable logic array of claim 11, wherein the MUX driver comprises a sense amplifier configured to detect a voltage level on the first row and to generate a binary output voltage based on a comparison of the voltage level on the first row to a threshold voltage.

13. The programmable logic array of claim 11, wherein the MUX driver comprises a write portion configured to couple the MTJ in the output plane to one of the plurality of programmable sources associated with the output plane.

14. The programmable logic array of claim 13, wherein one of the plurality of programmable sources is coupled to a column coupled to the MTJ in the output plane.

15. The programmable logic array of claim 1, further comprising:

an output sense amplifier coupled to the output plane configured to detect a voltage level on a column of the output plane and to generate a binary output voltage based on a comparison of the voltage level on the column of the output plane to a threshold voltage.

16. A method for implementing logic in an array comprising:

programming each of a plurality of spin transfer torque magnetic tunnel junction (MTJ) devices, arranged in an array to either a high or low resistance state, wherein each MTJ device is programmed by a first programmable source coupled to a free layer side of a selected MTJ device and programmable source coupled to a fixed layer side of the selected MTJ device;

arranging a first group of the MTJ devices into columns and rows of an input plane;

arranging a second group of the MTJ devices into at least one column in an output plane, wherein outputs of each row are coupled the MTJ devices in the at least one column; and

determining a logic function based on the relative resistances of each MTJ device.

17. The method of claim 16, further comprising:

coupling a plurality of inputs, each input coupled to at least one MTJ device in corresponding input columns in the input plane;

coupling a plurality of MTJ devices from different input columns to a first row in an input plane, wherein a first programmable source from the programmable sources is coupled to the row;

generating a voltage on the first row by enabling the plurality of inputs and setting the first programmable source to a low voltage state; and

generating a binary output voltage based on a comparison of the voltage on the first row to a threshold voltage.

18. The method of claim 16, further comprising:

coupling output voltages of rows in the input plane to corresponding MTJ devices in a first column in the output plane;

setting a programmable source coupled to the first column in the output plane to a low voltage state to establish a voltage on the first output column; and

generating a binary output voltage for the output plane based on a comparison of the voltage on the first column in the output plane to a threshold voltage.

19. The method of claim 16 comprising:

reconfiguring a logic function realized by at least one of the input plane or output plane by reprogramming each of the plurality of spin transfer torque magnetic tunnel junction (MTJ) devices in the one of the input plane or output plane.

20. The method of claim 19, wherein the reconfiguring the logic function comprises changing the resistance state of each of the plurality of spin transfer torque magnetic tunnel junction (MTJ) devices in the one of the input plane or output plane.