Interface circuit

• US 20080238491A1
• Filed: 03/28/2008
• Published: 10/02/2008
• Est. Priority Date: 03/30/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: AIZAWA, Hiroyuki
• Granted Patent: US 8,040,144 B2
• Time in Patent Office: Days
• US Class Current: 327/65
• CPC Class Codes: H03K 19/0185 using field effect transistors only

Abstract

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

Claims

1. An interface circuit comprising:

a reference voltage generation circuit to generate a reference voltage;

a differential voltage signal generation circuit to convert send data input in sending data in to pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit;

a receiver to convert a pair of differential voltage signals input in receiving data and output received data; and

a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

2. The interface circuit according to claim 1 wherein the resistance circuit includes first resistance circuits to generate a pair of differential voltage signals having a potential difference being a first value corresponding to a sensitivity specification necessary for the receiver and second resistance circuits to generate a pair of differential voltage signals having a potential difference being a second value smaller than the sensitivity specification.

3. The interface circuit according to claim 1 wherein the receiver test circuit includes:

first resistance circuits to generate a pair of differential voltage signals having a potential difference being a first value corresponding to a sensitivity specification being necessary for the receiver;

second resistance circuits to generate a pair of differential voltage signals having a potential difference being a second value smaller than the sensitivity specification;

a selector to select the first resistance circuits or the second resistance circuits at test timing; and

a switch to connect the first resistance circuits or the second resistance circuits to the differential voltage signal generation circuit through the selector at the test timing.

4. The interface circuit according to claim 2 wherein the first resistance circuits generate differential voltage signals having potential difference indicating squelch, and the second resistance circuits generate differential voltage signals having potential difference determined as normal signal.

5. The interface circuit according to claim 3 wherein the first resistance circuits generate differential voltage signals having potential difference indicating squelch, and the second resistance circuits generate differential voltage signals having potential difference determined as normal signal.

6. The interface circuit according to claim 4 wherein the receiver includes:

a receiver circuit to convert the pair of differential voltage signals and output the received data; and

a squelch detection circuit to detect squelch condition.

7. The interface circuit according to claim 5 wherein the receiver further includes a mask circuit to output a logical addition of the squelch detection circuit and the receiver circuit.

8. The interface circuit according to claim 1 wherein the resistance circuit includes a resistor conditioning circuit capable of conditioning a resistance value or a variable resistor capable of setting a resistance value from an external device.

9. The interface circuit according to claim 2 wherein the resistance circuit includes a resistor conditioning circuit capable of conditioning a resistance value or a variable resistor capable of setting a resistance value from an external device.

10. The interface circuit according to claim 3 wherein the resistance circuit includes a resistor conditioning circuit capable of conditioning a resistance value or a variable resistor capable of setting a resistance value from an external device.

11. The interface circuit according to claim 4 wherein the resistance circuit includes a resistor conditioning circuit capable of conditioning a resistance value or a variable resistor capable of setting a resistance value from an external device.

12. The interface circuit according to claim 1 wherein the differential voltage signal generation circuit includes a first current driven driver to which the send data is input, a inverter to invert the send data and a second current driven driver to which the send data inverted by the inverter is input.

13. The interface circuit according to claim 2 wherein the differential voltage signal generation circuit includes a first current driven driver to which the send data is input, a inverter to invert the send data and a second current driven driver to which the send data inverted by the inverter is input.

14. The interface circuit according to claim 3 wherein the differential voltage signal generation circuit includes a first current driven driver to which the send data is input, a inverter to invert the send data and a second current driven driver to which the send data inverted by the inverter is input.

15. The interface circuit according to claim 4 wherein the differential voltage signal generation circuit includes a first current driven driver to which the send data is input, a inverter to invert the send data and a second current driven driver to which the send data inverted by the inverter is input.

16. The interface circuit according to claim 1 further comprising:

a send data generation circuit to generate a send data for test; and

a send data check circuit to compare the send data generated by the send data generation circuit with the received data output from the receiver and determine a pass or failure of the receiver based on the comparison result.

17. The interface circuit according to claim 2 further comprising:

a send data generation circuit to generate a send data for test; and

a send data check circuit to compare the send data generated by the send data generation circuit with the received data output from the receiver and determine a pass or failure of the receiver based on the comparison result.

18. The interface circuit according to claim 3 further comprising:

a send data generation circuit to generate a send data for test; and

a send data check circuit to compare the send data generated by the send data generation circuit with the received data output from the receiver and determine a pass or failure of the receiver based on the comparison result.

19. The interface circuit according to claim 4 further comprising:

a send data generation circuit to generate a send data for test; and

a send data check circuit to compare the send data generated by the send data generation circuit with the received data output from the receiver and determine a pass or failure of the receiver based on the comparison result.