Power-up signal generating circuit and method for driving the same

• US 20080238500A1
• Filed: 12/31/2007
• Published: 10/02/2008
• Est. Priority Date: 03/31/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jung, Ho-Don
• Granted Patent: US 7,675,331 B2
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A power-up signal generating circuit that prevents repeatedly generating a power-up signal even when there is noise on an external voltage. The power-up signal generating circuit includes a level detector, a level comparator, and a reentry protector. The level detector is configured to deactivate a first level detection signal when a level of an external voltage increases above a upper limit reference voltage. The level comparator is configured to deactivate a second level detection signal when the level of the external voltage increases above a lower limit reference voltage. The reentry protector is configured to activate the power-up signal in response to the second level detection signal and deactivate the power-up signal in response to a deactivation of the first level detection signal.

Claims

1. A power-up signal generating circuit, comprising:

a level detector configured to deactivate a first level detection signal when a level of an external voltage increases above a first reference voltage;

a level comparator configured to deactivate a second level detection signal when the level of the external voltage increases above a second reference voltage; and

a reentry protector configured to activate a power-up signal in response to the second level detection signal and deactivate the power-up signal in response to a deactivation of the first level detection signal.

2. The power-up signal generating circuit as recited in claim 1, wherein the reentry protector includes:

a first inverter configured to invert the second level detection signal;

an RS latch configured to receive the first level detection signal as a set signal and an output signal of the first inverter as a reset signal; and

a second inverter configured to invert an output signal of the RS latch to output the power-up signal.

3. The power-up signal generating circuit as recited in claim 2, wherein the RS latch includes a first NAND gate and a second NAND gate cross-coupled to each other.

4. The power-up signal generating circuit as recited in claim 1, further comprising a voltage divider configured to divide the external voltage to output a divided voltage, wherein the level detector and the level comparator are configured to receive the divided voltage as the external voltage.

5. The power-up signal generating circuit as recited in claim 1, wherein the level of the second reference voltage is lower than that of the first reference voltage.

6. The power-up signal generating circuit as recited in claim 4, wherein the level comparator includes:

a differential amplifier configured to receive a voltage corresponding to the second reference voltage and the divided voltage as a differential input; and

a third inverter configured to invert an output signal of the differential amplifier to output the second level detection signal.

7. The power-up signal generating circuit as recited in claim 6, wherein the level detector includes:

a PMOS transistor having a gate connected to a ground voltage terminal, a source connected to an external voltage terminal, and a drain connected to an output node;

an NMOS transistor having a gate receiving the divided voltage, a drain connected to the output node, and a source connected to the ground voltage terminal; and

a buffer configured to buffer a voltage of the output node to output the first level detection signal.

8. The power-up signal generating circuit as recited in claim 7, wherein the voltage divider includes a first resistor and a second resistor connected in series between the external voltage terminal and the ground voltage terminal and outputs a voltage applied to a common node of the first and second resistors as the divided voltage.

9. The power-up signal generating circuit as recited in claim 8, further including a reference voltage generator configured to generate the voltage corresponding to the second reference voltage.

10. A method for driving a power-up signal generating circuit, the method comprising:

detecting a level of an external voltage;

deactivating a power-up signal, a level of which follows the level of the external voltage when activated, to a ground voltage level when the level of the external voltage increases above a first reference voltage; and

reactivating the power-up signal when the level of the external voltage falls below a second reference voltage, wherein the second reference voltage has a level lower than the first reference voltage.

11. The method as recited in claim 10, further comprising:

making the power-up signal following the level of the external voltage when the level of the external voltage is lower than that of the first reference voltage at an initial operation.

12. A power-up signal generating circuit, comprising:

a first pre-signal generating unit configured to deactivate a first level detection signal when a level of a signal corresponding to an external voltage increases above a first reference voltage;

a second pre-signal generating unit configured to deactivate a second level detection signal when the level of the signal increases above a second reference voltage; and

a main signal generating unit configured to activate a power-up signal in response to an activation of the second level detection signal, and deactivate the power-up signal in response to a deactivation of the first level detection signal.

13. The power-up signal generating circuit as recited in claim 12, wherein the first pre-signal generating unit includes:

a voltage divider configured to divide the external voltage to output a first divided voltage; and

a level detector configured to detect a level of the first divided voltage and deactivate the first level detection signal when the level of the first divided voltage increases above the first reference voltage.

14. The power-up signal generating circuit as recited in claim 13, wherein the second pre-signal generating unit includes:

a level comparator configured to deactivate the second level detection signal when the level of a divided voltage, which is one of the first divided voltage and a second divided voltage output by a second voltage divider configured to divide the external voltage, increases above the second reference voltage.

15. The power-up signal generating circuit as recited in claim 14, further including a reference voltage generating unit configured to generate the second reference voltage.

16. The power-up signal generating circuit as recited in claim 15, wherein the level of the second reference voltage is lower than that of the first reference voltage.

17. The power-up signal generating circuit as recited in claim 16, wherein the main signal generating unit includes:

a first inverter configured to invert the second level detection signal;

an RS latch configured to receive the first level detection signal as a set signal and an output signal of the first inverter as a reset signal; and

a second inverter configured to invert an output signal of the RS latch to output the power-up signal.

18. The power-up signal generating circuit as recited in claim 17, wherein the level comparator includes:

a differential amplifier configured to receive the second reference voltage and the divided voltage as a differential input; and

a third inverter configured to invert an output signal of the differential amplifier to output the second level detection signal.

19. The power-up signal generating circuit as recited in claim 18, wherein the level detector includes:

a PMOS transistor having a gate connected to a ground voltage terminal, a source connected to an external voltage terminal, and a drain connected to an output node;

an NMOS transistor having a gate receiving the divided voltage, a drain connected to the output node, and a source connected to the ground voltage terminal; and

a buffer configured to buffer a voltage of the output node to output the first level detection signal.