Semiconductor Device

• US 20080238533A1
• Filed: 01/24/2005
• Published: 10/02/2008
• Est. Priority Date: 01/30/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Granted Patent: US 7,707,442 B2
• Time in Patent Office: Days
• US Class Current: 327/535
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A semiconductor device capable of stabilizing power supply by suppressing power consumption as much as possible. The semiconductor device of the invention includes a central processing unit having a plurality of units and a control circuit, and an antenna. The control circuit includes a means for outputting, based on a power supply signal including data on power supply from an antenna (through an antenna) or a load signal obtained by an event signal supplied from each of the units, one or more of a first control signal for stopping power supply to one or more of the units, a second control signal for varying a power supply potential supplied to one or more of the units, and a third control signal for stopping supplying a clock signal to one or more of the units.

Claims

1. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit; and

a clock generation circuit,

wherein the control circuit outputs to at least one of the power supply circuit and the clock generation circuit, based on a power supply signal including data on power supply from the antenna, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a glass substrate,

wherein the plurality of units and the control circuit are provided over the glass substrate.

6. The semiconductor device according to any one of claims 1 to 4, further comprising a flexible substrate,

wherein the plurality of units and the control circuit are provided over the flexible substrate.

7. The semiconductor device according to any one of claims 1 to 4,

wherein the plurality of units are selected from a bus interface, a data cache, an instruction decoder, a reservation station, an instruction cache, an arithmetic logical unit, a floating point unit, a branch unit, a load/store unit, and a general purpose register.

8. The semiconductor device according to any one of claims 1 to 4,

wherein the plurality of units are selected from a pipeline unit, a peripheral memory controller, and a peripheral bus controller.

2. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit;

a clock generation circuit;

a plurality of first switches provided between the plurality of units and the power supply circuit, wherein each of the plurality of first switches corresponds to one of the plurality of units; and

a plurality of second switches provided between the plurality of units and the clock generation circuit, wherein each of the plurality of second switches corresponds to one of the plurality of units,

wherein the control circuit outputs to at least one of the first switches and the second switches, based on a power supply signal including data on power supply from the antenna, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units.

3. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit; and

a clock generation circuit,

wherein the control circuit outputs to at least one of the power supply circuit and the clock generation circuit, based on a load signal obtained by an event signal supplied from each of the units, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units.

4. A semiconductor device comprising:

a central processing unit including a plurality of units and a control circuit;

an antenna;

a power supply circuit;

a clock generation circuit;

a plurality of first switches provided between the plurality of units and the power supply circuit, wherein each of the plurality of first switches corresponds to one of the plurality of units; and

a plurality of second switches provided between the plurality of units and the clock generation circuit, wherein each of the plurality of second switches corresponds to one of the plurality of units,

wherein the control circuit outputs to at least one of the first switches and the second switches, based on a load signal obtained by an event signal supplied from each of the units, at least one of a first control signal for stopping power supply to at least one of the units, a second control signal for varying a power supply potential supplied to at least one of the units, and a third control signal for stopping supplying a clock signal to at least one of the units.

9. A semiconductor device comprising:

a plurality of memory blocks;

a control circuit; and

a power supply circuit,

wherein each of the memory blocks comprises;

a memory cell array including a plurality of memory cells each having a memory element in a region where a bit line and a word line cross each other with an insulator interposed there between; and

a row decoder connected to the word line; and

the control circuit outputs to the power supply circuit, based on an operation signal including operating data of the memory blocks, at least one of a first control signal for varying a power supply potential supplied to the memory cell array, and a second control signal for stopping a power supply potential supplied to the row decoder.

10. A semiconductor device comprising:

a plurality of memory blocks;

a control circuit;

a power supply circuit; and

a plurality of switches provided between the memory blocks and the power supply circuit, wherein each of the plurality of switches corresponds to one of the plurality of memory blocks,

wherein each of the memory blocks comprises;

a memory cell array including a plurality of memory cells each having a memory element in a region where a bit line and a word line cross each other with an insulator interposed there between; and

a row decoder connected to the word line; and

the control circuit outputs to the switches, based on an operation signal including operating data of the memory blocks, at least one of a first control signal for varying a power supply potential supplied to the memory cell array, and a second control signal for stopping a power supply potential supplied to the row decoder.

11. The semiconductor device according to any one of claims 9 and 10, further comprising a central processing unit for outputting the operation signal.

12. The semiconductor device according to any one of claims 9 and 10, further comprising a dedicated circuit for outputting the operation signal.

13. The semiconductor device according to any one of claims 9 and 10, further comprising a glass substrate,

wherein the plurality of memory blocks and the control circuit are provided over the glass substrate.

14. The semiconductor device according to any one of claims 9 and 10, further comprising a flexible substrate,

wherein the plurality of memory blocks and the control circuit are provided over the flexible substrate.

15. The semiconductor device according to any one of claims 9 and 10,

wherein the memory cells included in the memory blocks and provided in the same column are connected to the same bit line.

16. The semiconductor device according to any one of claims 9 and 10,

wherein the memory cells included in the memory blocks are connected to the same column decoder.

17. The semiconductor device according to any one of claims 9 and 10,

wherein each of the memory blocks comprises a column decoder that operates independently of each other.

18. The semiconductor device according to any one of claims 9 and 10,

wherein the bit line is provided independently for each of the memory blocks.

19. The semiconductor device according to any one of claims 9 and 10,

wherein the word line is provided independently for each of the memory blocks.

20. The semiconductor device according to any one of claims 9 and 10,

wherein each of the memory blocks is selected from the group of a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), an FRAM (Ferroelectric Random Access Memory), a mask ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Electrically Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), and a flash memory.