Substrate including wiring for transmitting signal, apparatus and system including the substrate

• US 20080238585A1
• Filed: 03/26/2008
• Published: 10/02/2008
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Tokoro, Tomokazu
• Granted Patent: US 8,072,774 B2
• Time in Patent Office: Days
• US Class Current: 333/247
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01P 3/08 Microstrips; Strip lines
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/09236 Parallel layout layout of balanced signal pairs H05K1/0245; superposed layout H05K2201/09672
• CPC Class Codes: H05K 2201/09336 Signal conductors in same plane as power plane
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias redundant conductors or connections H05K2201/0979
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236

Abstract

An apparatus includes a substrate which includes an electronic component mounted on the substrate, the electronic component for processing a pair of signals, the substrate including a first wire for transmitting one of the signals, the first wire being formed on a first layer of the substrate, and a second wire for transmitting another one of the signals, the second wire being formed on a second layer of the substrate in a first region under the electronic component and being formed on a third layer in a second region of an other part of the first region.

Claims

1. An apparatus, comprising:

a substrate which includes an electronic component mounted on said substrate, said electronic component for processing a pair of signals,

wherein said substrate comprises;

a first wire for transmitting one of said signals, said first wire being formed on a first layer of said substrate; and

a second wire for transmitting another one of said signals, said second wire being formed on a second layer of said substrate in a first region under said electronic component and being formed on a third layer in a second region of an other part of said first region.

2. The apparatus according to claim 1, wherein said first wire comprises a first width in said first region and comprises a second width thicker than said first width in said second region, and

wherein said second wire comprises a third width in said first region and comprises a fourth width thicker than said third width in said second region.

3. The apparatus according to claim 1, wherein said first wire and said second wire are formed substantially parallel with respect to a direction of a thickness of said substrate.

4. The apparatus according to claim 1, wherein said substrate further comprises:

an internal through hole which connects said first wire and said second wire, said internal through hole being formed inside of said substrate between said first layer and said second layer.

5. The apparatus according to claim 1, wherein said substrate further comprises:

a first ground layer being formed on said third layer in said first region except said second region; and

a second ground layer being formed on said second layer in said second region except said first region.

6. The apparatus according to claim 5, wherein said substrate further comprises:

a third ground layer being formed on a fourth layer of said substrate,

wherein said first layer and said second layer are formed between said third layer and said fourth layer.

7. The apparatus according to claim 6, wherein said substrate comprises a first thickness between said first layer and said second layer so that a first impedance of each of said first wire and said second wire comprises a predetermined value, said first wire and said second wire being formed in said first region,

wherein said substrate comprises a second thickness between said second layer and said third layer so that a second impedance of said second wire formed in said second region comprises said predetermined value, and

wherein said substrate comprises a third thickness between said first layer and said fourth layer so that a third impedance of said first wire formed in said second region comprises said predetermined value.

8. A substrate for mounting an electronic component, said electronic component for processing a pair of signals, said substrate comprising:

a first wire for transmitting one of said signals, said first wire being formed on a first layer of said substrate; and

a second wire for transmitting another one of said signals, said second wire being formed on a second layer of said substrate in a first region under said electronic component and being formed on a third layer in a second region of an other part of said first region.

9. The substrate according to claim 8, wherein said first wire comprises a first width in said first region and comprises a second width thicker than said first width in said second region, and

wherein said second wire comprises a third width in said first region and comprises a fourth width thicker than said third width in said second region.

10. The substrate according to claim 8, wherein said first wire and said second wire are formed substantially parallel with respect to a direction of a thickness of said substrate.

11. The substrate according to claim 8, further comprising:

an internal through hole which connects said first wire and said second wire, said internal through hole being formed inside of said substrate between said first layer and said second layer.

12. The substrate according to claim 8, further comprising:

a first ground layer being formed on said third layer in said first region except said second region; and

a second ground layer being formed on said second layer in said second region except said first region.

13. The substrate according to claim 12, further comprising:

a third ground layer being formed on a fourth layer of said substrate, and

wherein said first layer and said second layer are formed between said third layer and said fourth layer.

14. The substrate according to claim 13, wherein said substrate comprises a first thickness between said first layer and said second layer so that a first impedance of each of said first wire and said second wire comprises a predetermined value, said first wire and said second wire being formed in said first region,

wherein said substrate comprises a second thickness between said second layer and said third layer so that a second impedance of said second wire formed in said second region comprises said predetermined value, and

wherein said substrate comprises a third thickness between said first layer and said fourth layer so that a third impedance of said first wire formed in said second region comprises said predetermined value.

15. A system, comprising:

a substrate which includes an electronic component mounted on said substrate, said electronic component for processing a pair of signals,

wherein said substrate comprises;

a first wire for transmitting one of said signals, said first wire being formed on a first layer of said substrate; and

a second wire for transmitting another one of said signals, said second wire being formed on a second layer of said substrate in a first region under said electronic component and being formed on a third layer in a second region of an other part of said first region.

16. The system according to claim 15, wherein said first wire comprises a first width in said first region and comprises a second width thicker than said first width in said second region, and

wherein said second wire comprises a third width in said first region and comprises a fourth width thicker than said third width in said second region.

17. The system according to claim 15, wherein said first wire and said second wire are formed substantially parallel with respect to a direction of a thickness of said substrate.

18. The system according to claim 15, wherein said substrate further comprises:

an internal through hole which connects said first wire and said second wire, said internal through hole being formed inside of said substrate between said first layer and said second layer.

19. The system according to claim 15, wherein said substrate further comprises:

a first ground layer being formed on said third layer in said first region except said second region; and

a second ground layer being formed on said second layer in said second region except said first region.

20. The system according to claim 19, wherein said substrate further comprises:

a third ground layer being formed on a fourth layer of said substrate,

wherein said first layer and said second layer are formed between said third layer and said fourth layer.

21. The system according to claim 20, wherein said substrate comprises a first thickness between said first layer and said second layer so that a first impedance of each of said first wire and said second wire comprises a predetermined value, said first wire and said second wire being formed in said first region,

wherein said substrate comprises a second thickness between said second layer and said third layer so that a second impedance of said second wire formed in said second region comprises said predetermined value, and

wherein said substrate comprises a third thickness between said first layer and said fourth layer so that a third impedance of said first wire formed in said second region comprises said predetermined value.