Chip scale power converter package having an inductor substrate

• US 20080238599A1
• Filed: 03/27/2007
• Published: 10/02/2008
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Sun, Ming, Hebert, Francois
• Granted Patent: US 8,058,960 B2
• Time in Patent Office: Days
• US Class Current: 336/110
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/1902 including thick film passive components
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49075 including permanent magnet or core

Abstract

A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.

Claims

1. A power converter package comprising:

an inductor substrate; and

a power integrated circuit bonded onto the inductor substrate.

2. The converter according to claim 1, wherein the inductor substrate comprises a planar spiral inductor formed thereon.

3. The power converter according to claim 2, wherein the planar spiral inductor has a thickness greater than 17 microns.

4. The power converter according to claim 2, further comprising a magnetic core layer disposed under the planar spiral inductor.

5. The power converter according to claim 2, further comprising a magnetic core layer disposed over the planar spiral inductor.

6. The power converter according to claim 2, further comprising a first magnetic core layer disposed under the planar spiral inductor and a second magnetic core layer disposed over the planar spiral inductor, the first and second magnetic core layers being coupled by means of a magnetic core material via.

7. The power converter according to claim 2, wherein the power integrated circuit comprises a plurality of contacts coupled to a plurality of peripheral contacts on the inductor substrate by means of a cross over metal layer.

8. The power converter according to claim 2, wherein the power integrated circuit is flip chip bonded onto the inductor substrate.

9. A chip scale inductor substrate comprising:

a high resistivity substrate; and

a planar spiral inductor formed on the substrate.

10. The chip scale inductor substrate according to claim 9, wherein the planar spiral inductor has a thickness greater than 17 microns.

11. The chip scale inductor substrate according to claim 9, further comprising a plurality of magnetic core layers sandwiched by dielectric layers disposed under the planar spiral inductor.

12. The chip scale inductor substrate according to claim 11, further comprising a magnetic core layer disposed over the planar spiral inductor.

13. The chip scale inductor substrate according to claim 9, further comprising a first magnetic core layer disposed under the planar spiral inductor and a second magnetic core layer disposed over the planar spiral inductor, the first and second magnetic core layers being coupled by means of a magnetic core material via.

14. The chip scale inductor substrate according to claim 9, wherein the inductor substrate comprises a plurality of contacts in a center area of the inductor substrate coupled to a plurality of peripheral contacts on the inductor substrate by means of a cross over metal layer.

15. The chip scale inductor substrate according to claim 9, further comprising a low-K dielectric material disposed under the planar spiral inductor to reduce parasitic capacitance.

16. A method of fabricating a chip scale power converter package comprising the steps of:

providing a substrate;

fabricating a plurality of planar spiral inductors on the substrate to form a plurality of inductor substrates;

bonding an integrated circuit onto each inductor substrate; and

dicing the plurality of inductor substrates.

17. The method according to claim 16, further comprising forming a first oxide layer on the high resistivity substrate before the fabrication step.

18. The method according to claim 17, further comprising depositing a first magnetic core material layer on the oxide layer before the fabrication step.

19. The method according to claim 18, further comprising depositing a second oxide layer on the magnetic core material layer before the fabrication step.

20. The method according to claim 19, further comprising depositing a cross over metal layer on the second oxide layer before the fabrication step.

21. The method according to claim 20, further comprising depositing a third oxide layer over the cross over metal layer before the fabrication step.

22. The method according to claim 21, further comprising depositing a dielectic material over the third oxide layer before the fabrication step.

23. The method according to claim 22, further comprising forming vias to the cross over metal layer before the fabrication step.

24. The method according to claim 23, further comprising etching exposed portions of the third oxide layer before the fabrication step.

25. The method according to claim 24, further comprising depositing a barrier metal layer on the dielectic material and exposed portions of the cross over metal layer before the fabrication step.

26. The method according to claim 25, further comprising depositing a seed layer on the barrier metal layer before the fabrication step.

27. The method according to claim 26, wherein the fabrication step comprises plating the plurality of planar spiral inductors.

28. The method according to claim 27, wherein the fabrication step comprises patterning the plurality of planar spiral inductors.

29. The method according to claim 28, further comprising etching exposed portions of the barrier metal and seed layers.

30. The method according to claim 29, further comprising depositing a first passivation layer.

31. The method according to claim 30, further comprising forming a peripheral via reaching the first magnetic core material layer.

32. The method according to claim 31, further comprising depositing a second magnetic core material layer.

33. The method according to claim 32, further comprising depositing a second passivation layer.

34. The method according to claim 33, further comprising forming contact pads in the vias.

35. The method according to claim 34, further comprising forming solder balls on the contact pads.