REFERENCE VOLTAGE SHIFTING TECHNIQUE FOR OPTIMIZING SNR PERFORMANCE IN PIPELINE ADCS WITH RESPECT TO INPUT SIGNAL

• US 20080238737A1
• Filed: 03/29/2007
• Published: 10/02/2008
• Est. Priority Date: 03/29/2007
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Abugharbieh, Khaldoon, Jing, Ping
• Granted Patent: US 7,535,399 B2
• Time in Patent Office: Days
• US Class Current: 341/110
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, where the threshold and reference voltages of the first set are shifted with respect to corresponding threshold and reference voltages of the second set. The second circuit may be configured to generate a digital output signal in response to the plurality of digital intermediate signals.

Claims

1. An apparatus comprising:

a first circuit configured to generate a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold reference voltages, wherein the threshold and reference voltages of said first set are shifted with respect to corresponding threshold and reference voltages of said second set; and

a second circuit configured to generate a digital output signal in response to the plurality of digital intermediate signals.

2. The apparatus according to claim 1, wherein said second circuit comprises an error correction circuit.

3. The apparatus according to claim 1, wherein said first circuit comprises a plurality of stages, each stage configured to generate one of said plurality of digital intermediate signals.

4. The apparatus according to claim 3, wherein each of said plurality of stages comprises a 1.5 bit stage.

5. The apparatus according to claim 3, wherein said first circuit further comprises a flash analog-to-digital converter (ADC) coupled to an output of one of said plurality of stages and configured to generate one of said plurality of digital intermediate signals.

6. The apparatus according to claim 5, wherein said flash analog-to-digital converter (ADC) comprises a 2-bit flash ADC.

7. The apparatus according to claim 3, wherein each of said plurality of stages comprises:

a sample and hold circuit configured to sample an input signal;

a sub-ADC configured to generate one of the digital intermediate signals by converting the sample of the input signal from the sample and hold circuit from the analog domain to the digital domain;

a digital-to-analog converter (DAC) configured to convert the digital intermediate signal from the sub-ADC from the digital domain back to the analog domain;

an adder configured to generate a residue signal in response to the sample of the input signal from the sample and hold circuit and an output of the DAC; and

an amplifier configured to generate a residual output signal in response to the residue signal.

8. The apparatus according to claim 3, wherein each of said plurality of stages comprises:

a first comparator circuit configured to generate a first control signal in response to an input signal and a first threshold voltage;

a second comparator circuit configured to generate a second control signal in response to the input signal and a second threshold voltage;

a latch circuit configured to generate and store an output signal in response to the first control signal and the second control signal;

a multiplexer configured to select between a plurality of voltage levels in response to the output signal of the latch circuit; and

an amplifier configured to generate a residual output signal in response to the input signal, an output of the multiplexer and the residual output signal.

9. The apparatus according to claim 8, wherein a first one of said plurality of stages is configured such that:

said first threshold voltage comprises one and one-fourth times a predefined reference voltage;

said second threshold voltage comprises three-fourths times said predefined reference voltage; and

said multiplexer selects between said predefined reference voltage, a voltage level equal to twice said predefined reference voltage and a voltage level equal to three times said predefined reference voltage.

10. The apparatus according to claim 9, wherein each of said plurality of stages after said first stage is configured such that:

said first threshold voltage comprises one-fourth times said predefined reference voltage;

said second threshold voltage comprises one-fourth times a negative version of said predefined reference voltage; and

said multiplexer selects between said predefined reference voltage, said negative version of said predefined reference voltage and a voltage level equal to zero.

11. The apparatus according to claim 1, wherein said analog signal comprises a dc-coupled signal.

12. An apparatus comprising:

means for generating a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, wherein the threshold and reference voltages of said first set are shifted with respect to corresponding threshold and reference voltages of said second set; and

means for generating a digital output signal in response to the plurality of digital intermediate signals.

13. A method of reference voltage shifting in a pipeline ADC comprising the steps of:

generating a plurality of digital intermediate signals in response to an analog input signal, a first set of threshold and reference voltages and a second set of threshold and reference voltages, wherein the threshold and reference voltages of said first set are shifted with respect to corresponding threshold and reference voltages of said second set; and

generating a digital output signal in response to the plurality of digital intermediate signals.

14. The method according to claim 13, wherein the step of generating the digital output signal further comprises performing error correction.

15. The method according to claim 13, wherein said plurality of digital intermediate signals are generated using a plurality of stages.

16. The method according to claim 15, wherein one of said plurality of stages comprises a 2 bit flash analog to digital converter (ADC) and all remaining stages of said plurality of stages comprise 1.5 bit stages.

17. The method according to claim 16, wherein each of said 1.5 bit stages comprise:

a sample and hold circuit configured to sample an input signal;

a sub-ADC configured to generate one of the digital intermediate signals by converting the sample of the input signal from the sample and hold circuit from the analog domain to the digital domain;

a digital-to-analog converter (DAC) configured to convert the digital intermediate signal from the sub-ADC from the digital domain back to the analog domain;

an adder configured to generate a residue signal in response to the sample of the input signal from the sample and hold circuit and an output of the DAC; and

an amplifier configured to generate a residual output signal in response to the residue signal.

18. The method according to claim 16, wherein each of said 1.5 bit stages comprise:

a first comparator circuit configured to generate a first control signal in response to an input signal and a first threshold voltage;

a second comparator circuit configured to generate a second control signal in response to the input signal and a second threshold voltage;

a latch circuit configured to generate and store an output signal in response to the first control signal and the second control signal;

a multiplexer configured to select between a plurality of voltage levels in response to the output signal of the latch circuit; and

an amplifier configured to generate a residual output signal in response to the input signal, an output of the multiplexer and the residual output signal.

19. The method according to claim 18, wherein a first one of said 1.5 bit stages is configured such that:

said first threshold voltage comprises one and one-fourth times a predefined reference voltage;

said second threshold voltage comprises three-fourths times said predefined reference voltage; and

said multiplexer selects between said predefined reference voltage, a voltage level equal to twice said predefined reference voltage and a voltage level equal to three times said predefined reference voltage.

20. The method according to claim 19, wherein each of the 1.5 bit stages after the first 1.5 bit ADC stage is configured such that:

said first threshold voltage comprises one-fourth times said predefined reference voltage;

said second threshold voltage comprises one-fourth times a negative version of said predefined reference voltage; and

said multiplexer selects between said predefined reference voltage, said negative version of said predefined reference voltage and a voltage level equal to zero.