NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM

• US 20080239812A1
• Filed: 03/28/2008
• Published: 10/02/2008
• Est. Priority Date: 03/30/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Futatsuyama, Takuya, ABIKO, Naofumi
• Granted Patent: US 7,649,776 B2
• Time in Patent Office: Days
• US Class Current: 365/185.12
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to readout data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.

Claims

1. A nonvolatile semiconductor memory system comprising:

a nonvolatile semiconductor memory having;

a plurality of NAND cell units having;

a memory cell string that includes a plurality of memory cell transistors that are connected in series and capable of electrically rewriting data and storing data having two or more values represented by a threshold voltage thereof;

a first select transistor that is connected between one end of the memory cell string and a source line; and

a second select transistor that is connected between the other end of the memory cell string and a bit line,

a plurality of word lines that are connected to a gate electrode of one of the memory cell transistors in each of the NAND cell units, the plurality of word lines including a first word line that is adjacent to the first select transistor;

a first select gate line that is connected to a gate electrode of the first select transistor in each of the NAND cell units;

a second select gate line that is connected to a gate electrode of the second select transistor in each of the NAND cell units;

a row controller that selectively applies a read voltage to the word lines, the first select gate line, and the second select gate line; and

a memory controller having;

a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory;

a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and

a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to the first word line;

wherein the row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating the data stored in the memory cell transistors.

2. The memory system according to claim 1, wherein the plurality of word lines include a second word line that is adjacent to the second select transistor,

wherein the processor sets a read voltage based on the writing information to read out data from the memory cell transistors connected to the second word line, and

wherein the row controller is configured to set a plurality of level of the read voltage to be applied to the second word line, with respect to one threshold for discriminating the data stored in the memory cell transistors.

3. The memory system according to claim 1, wherein the row controller is configured to set a common read level to be applied to the plurality of word lines, with respect to one threshold for discriminating the data stored in the memory cell transistors, and

wherein the row controller is configured to set a corrected read level to be applied to the first word line, the corrected read level being higher than the common read level.

4. The memory system according to claim 3, wherein the processor selects the corrected read level based on the writing information to cope with a change of the threshold caused by the writing to the memory cell transistors.

5. The memory system according to claim 3, wherein the row controller is configured to set the correct read level to be applied to the second word line, the corrected read level being higher than the common read level.

6. The memory system according to claim 3, wherein the controller selects the corrected read level when the writing information indicates one of the memory cell transistors connected to one of the word lines except the first word line.

7. The memory system according to claim 3, wherein each of the NAND cell units includes an even page having a set of the memory cell transistors selected by one of the plurality of word lines and a portion of a plurality of bit lines and include an odd page having a set of the memory cell transistors selected by the one of word lines and the other portion of the plurality of bit lines,

wherein the memory cell transistor is configured to store one of 4-value data “

xy”

for each of the even page and the odd page, which is defined by upper page data “

x (x;

0 or

     1)” and

lower page data “

y (y;

0 or

     1)”

, and in which data “

11”

, data “

01”

, data “

00”

, and data “

10”

are assigned,

wherein the row controller is configured to perform data program and read operation at a time by a unit including a lower page of the even page, a lower page of the odd page, the upper page of the even page, and an upper page of the odd page,

wherein the row controller is configured to perform the program operation sequentially, for each of the plurality of memory cell transistors, in the order of the lower page of the even page, the lower page of the odd page, the upper page of the even page, and the upper page of the odd page,

wherein during a read operation for the lower page of the even page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the lower page of the odd page, the upper page of the even page, and the upper page of the odd page of the memory cell transistors connected to the first word line,

wherein during a read operation for the lower page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the even page and the upper page of the odd page of the memory cell transistors connected to the first word line, and

wherein during a read operation for the upper page of the even page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the odd page of the memory cell transistors connected to the first word line.

8. The memory system according to claim 3, wherein each of the NAND cell units includes an even page having a set of the memory cell transistors selected by one of the plurality of word lines and a portion of a plurality of bit lines and include an odd page having a set of the memory cell transistors selected by the one of word lines and the other portion of the plurality of bit lines,

wherein the memory cell transistor is configured to store one of 4-value data “

xy”

for each of the even page and the odd page, which is defined by upper page data “

x (x;

0 or

     1)” and

lower page data “

y (y;

0 or

     1)”

, and in which data “

11”

, data “

01”

, data “

00”

, and data “

10”

are assigned,

wherein the row controller is configured to perform data program and read operation at a time by a unit including a lower page of the even page, a lower page of the odd page, the upper page of the even page, and an upper page of the odd page,

wherein the row controller is configured to perform the program operation sequentially for the plurality of word lines, in the order of from the first word line to the second word line while data programming the memory cell transistors in the order of the lower page of the even page, the lower page of the odd page, the upper page of the even page, and the upper page of the odd page with respect to each of the plurality of word lines,

wherein during a read operation for the lower page of the even page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the lower page of the odd page, the upper page of the even page, and the upper page of the odd page of the memory cell transistors connected to the first word line,

wherein during a read operation for the lower page of the odd page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the even page and the upper page of the odd page of the memory cell transistors connected to the first word line, and

wherein during a read operation for the upper page of the even page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the odd page of the memory cell transistors connected to the first word line.

9. The memory system according to claim 5, wherein each of the NAND cell units includes an even page having a set of the memory cell transistors selected by one of the plurality of word lines and a portion of a plurality of bit lines and include an odd page having a set of the memory cell transistors selected by the one of word lines and the other portion of the plurality of bit lines,

wherein the memory cell transistor is configured to store one of 4-value data “

xy”

for each of the even page and the odd page, which is defined by upper page data “

x (x;

0 or

     1)” and

lower page data “

y (y;

0 or

     1)”

, and in which data “

11”

, data “

01”

, data “

00”

, and data “

10”

are assigned,

wherein the row controller is configured to perform data program and read operation at a time by a unit including a lower page of the even page, a lower page of the odd page, the upper page of the even page, and an upper page of the odd page,

wherein the row controller is configured to perform the program operation sequentially for the plurality of word lines, in the order of from the first word line to the second word line while data programming the memory cell transistors in the order of the lower page of the even page, the lower page of the odd page, the upper page of the even page, and the upper page of the odd page with respect to the plurality of the word lines,

wherein during a read operation for the lower page of the even page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the lower page of the odd page, the upper page of the even page, and the upper page of the odd page of the memory cell transistors connected to the first word line,

wherein during a read operation for the lower page of the odd page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the even page and the upper page of the odd page of the memory cell transistors connected to the first word line, and

wherein during a read operation for the upper page of the even page of the memory cell transistors connected to the first word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the odd page of the memory cell transistors connected to the first word line.

wherein during a read operation for the lower page of the even page of the memory cell transistors connected to the second word line, the processor selects the corrected read level in accordance with whether data is programmed into the lower page of the odd page, the upper page of the even page, and the upper page of the odd page of the memory cell transistors connected to the second word line,

wherein during a read operation for the lower page of the odd page of the memory cell transistors connected to the second word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the even page and the upper page of the odd page of the memory cell transistors connected to the second word line, and

wherein during a read operation for the upper page of the even page of the memory cell transistors connected to the second word line, the processor selects the corrected read level in accordance with whether data is programmed into the upper page of the odd page of the memory cell transistors connected to the second word line.

10. The memory system according to claim 9, wherein during read operations for the lower page before the upper page is programmed, a first read level is set in a voltage range between a threshold distribution of the memory cell transistor having data “

11” and

a threshold distribution of the memory cell transistor having data “

01”

,

wherein during read operations after the upper page is programmed, a second read level is set in a voltage range between a threshold distribution of the memory cell transistor having data “

11” and

a threshold distribution of the memory cell transistor having data “

01”

;

a third read level is set in a voltage range between a threshold distribution of the memory cell transistor having data “

01” and

a threshold distribution of the memory cell transistor having data “

00”

; and

a fourth read level is set in a voltage range between a threshold distribution of the memory cell transistor having data “

00” and

a threshold distribution of the memory cell transistor having data “

10”

,

wherein commonly for the plurality of word lines, a first common read voltage are set for the first read level,

wherein commonly for the plurality of word lines, a second common read voltage the second read level,

wherein commonly for the plurality of word lines, a third common read voltage are set for the third read level,

wherein commonly for the plurality of word lines, a fourth common read voltage are set for the fourth read level,

wherein for the first word line, a first corrected read voltage higher than the first common read voltage is set for the first read level;

a second corrected read voltage higher than the second common read voltage, a third corrected read voltage higher than the second corrected read voltage, and a fourth corrected read voltage higher than the third corrected read voltage are set for the second read level;

a fifth corrected read voltage higher than the third common read voltage, a sixth corrected read voltage higher than the fifth corrected read voltage, and a seventh corrected read voltage higher than the sixth corrected read voltage are set for the third read level; and

an eighth corrected read voltage higher than the fourth common read voltage, a ninth corrected read voltage higher than the eighth corrected read voltage, and a tenth corrected read voltage higher than the ninth corrected read voltage are set for the fourth read level,

wherein during a read operation for the lower page of the even page of the memory cell transistors connected to the first word line;

(a) the first common read voltage is selected when the lower page of the odd page of a first corresponding memory cell transistor connected to the first word line is not programmed;

(b) the first corrected read voltage is selected when the lower page of the odd page of the first corresponding memory cell transistor is programmed and when the upper page of the even page of a first given memory cell transistor is not programmed;

(c) the third common read voltage is selected when the upper page of the even page of the first given memory cell transistor is programmed and when the upper page of the odd page of the first corresponding memory cell transistor is not programmed;

(d) the fifth corrected read voltage is selected when the upper page of the odd page of the first corresponding memory cell transistor is programmed and when the upper page of the odd page of a third corresponding memory cell transistor connected to a third word line between the first word line and the second word line is not programmed;

(e) the sixth corrected read voltage is selected when the upper page of the odd page of the third corresponding memory cell transistor is programmed and when the upper page of the odd page of a fourth corresponding memory cell transistor connected to a fourth word line between the third word line and the second select gate line is not programmed; and

(f) the seventh common read voltage is selected when the upper page of the odd page of the fourth corresponding memory cell transistor is programmed,

11. The memory system according to claim 10, wherein during a read operation of the lower page of the odd page of the memory cell transistors connected to the first word line:

(a) the first common read voltage is selected when the upper page of the even page of the first given memory cell transistor is not programmed;

(b) the first corrected read voltage is selected when the upper page of the even page of the first given memory cell transistor is programmed and when the upper page of the odd page of the first corresponding memory cell transistor is not programmed;

(c) the third common read voltage is selected when the upper page of the odd page of the first corresponding memory cell transistor is programmed and when the upper page of the odd page of the third corresponding memory cell transistor is not programmed;

(d) the fifth corrected read voltage is selected when the upper page of the odd page of the third corresponding memory cell transistor is programmed and when the upper page of the odd page of the fourth corresponding memory cell transistor is not programmed;

(e) and the sixth corrected read voltage is selected when the upper page of the odd page of the fourth corresponding memory cell transistor line is programmed,

wherein during a read operation of the upper page of the even page of the memory cell transistors connected to the first word line line;

(a) the second common read voltage or the fourth common read voltage is selected when the upper page of the odd page of the first corresponding memory cell transistor is not programmed;

(b) the second corrected read voltage or the eighth corrected read voltage is selected when the upper page of the odd page of the first corresponding memory cell transistor is programmed and when the upper page of the odd page of the third corresponding memory cell transistor is not programmed;

(c) the third corrected read voltage or the ninth corrected read voltage is selected when the upper page of the odd page of the third corresponding memory cell transistor is programmed and when the memory cell transistors connected to the fourth word line is not programmed; and

(d) the fourth corrected read voltage or the tenth corrected read voltage is selected when at least one of the memory cell transistors connected to the fourth word line is programmed.

12. The memory system according to claim 11, wherein during a read operation of the upper page of the odd page of the memory cell transistors connected to the first word line:

(a) the second common read voltage or the fourth common read voltage is selected when the upper page of the odd page of the third corresponding memory cell transistor is not programmed;

(b) the second corrected read voltage or the eighth corrected read voltage is selected when the upper page of the odd page of the third corresponding memory cell transistor is programmed and when the upper page of the odd page of the fourth corresponding memory cell transistor is not programmed; and

(c) the third corrected read voltage or the ninth corrected read voltage is selected when the upper page of the odd page of the fourth corresponding memory cell transistor is programmed.

13. The memory system according to claim 12, wherein an eleventh corrected read voltage higher than the first common read voltage is applied to the second word line as the first read level,

wherein a twelfth corrected read voltage higher than the second common read voltage is applied to the second word line as the second read level,

wherein a thirteenth corrected read voltage higher than the third common read voltage is applied to the second word line as the third read level,

wherein a fourteenth corrected read voltage higher than the fourth common read voltage is applied to the second word line as the fourth read level, and

wherein during a read operation for the lower page of the even page of the memory cell transistors connected to the second word line:

(a) the first common read voltage is selected when the upper page of the odd page of the second corresponding memory cell transistor is not programmed;

(b) the eleventh corrected read voltage is selected when the lower page of the odd page of the second corresponding memory cell transistor is programmed and when the upper page of the even page of a second given memory cell transistor connected to the second word line is not programmed;

(c) the third common read voltage is selected when the upper page of the even page of the second given memory cell transistor is programmed and when the upper page of the odd page of the second corresponding memory cell transistor is not programmed; and

(d) the thirteenth corrected read voltage is selected when the upper page of the odd page of the second corresponding memory cell transistor is programmed.

14. The memory system according to claim 13, wherein during a read operation of the upper page of the odd page of the memory cell transistors connected to the second word line:

(a) the first common read voltage is selected when the upper page of the odd page of the second corresponding memory cell transistor is not programmed;

(b) the eleventh corrected read voltage is selected when the upper page of the even page of the second given memory cell transistor is programmed and when the upper page of the odd page of the corresponding memory cell transistor is not programmed; and

(c) the third common read voltage is selected when the upper page of the odd page of the second corresponding memory cell transistor is programmed,

wherein during a read operation of the upper page of the even page of the memory cell transistors connected to the second word line;

(a) the second common read voltage or the fourth common read voltage is selected when the upper page of the odd page of the second corresponding memory cell transistor is not programmed; and

(b) the twelfth corrected read voltage or the fourteenth corrected read voltage is selected when the upper page of the odd page of the second corresponding memory cell transistor is programmed.

15. The memory system according to claim 14, wherein during a read operation of the upper page of the odd page of the memory cell transistors connected to the first word line, the second common read voltage or the fourth common read voltage is selected.

16. The memory system according to claim 15, wherein the first corrected read voltage is set to the same values as the eleventh corrected read voltage,

wherein the second corrected read voltage is set to the same values as the twelfth corrected read voltage,

wherein the fifth corrected read voltage is set to the same values as the thirteenth corrected read voltage and the thirteenth corrected read voltage, and

wherein the eighth corrected read voltage is set to the same values as the fourteenth corrected read voltage.

17. The memory system according to claim1, wherein the memory included in the memory controller includes a FeRAM.

19. The memory system according to claim 18, wherein the memory system according to claim 1, wherein the plurality of word lines include a second word line that is adjacent to the second select transistor,

wherein the processor sets a read voltage based on the writing information to read out data from the memory cell transistors connected to the second word line, and

wherein the row controller is configured to set a plurality of level of the read voltage to be applied to the second word line, with respect to one threshold for discriminating the data stored in the memory cell transistors.

18. A nonvolatile semiconductor memory system comprising:

a nonvolatile semiconductor memory having;

a plurality of NAND cell units having;

a memory cell string that includes a plurality of memory cell transistors that are connected in series and capable of electrically rewriting data and storing data having two or more values represented by a threshold voltage thereof;

a first select transistor that is connected between one end of the memory cell string and a source line; and

a second select transistor that is connected between the other end of the memory cell string and a bit line,

a plurality of word lines that are connected to a gate electrode of one of the memory cell transistors in each of the NAND cell units, the plurality of word lines including a first word line that is adjacent to the first select transistor;

a first select gate line that is connected to a gate electrode of the first select transistor in each of the NAND cell units;

a second select gate line that is connected to a gate electrode of the second select transistor in each of the NAND cell units;

a row controller that selectively applies a read voltage to the word lines, the first select gate line, and the second select gate line; and

a memory controller having;

a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory;

a memory that stores writing information including elapsed times since the latest writing in each of the NAND cell units; and

a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to the first word line;

wherein the row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating the data stored in the memory cell transistors.

20. A nonvolatile semiconductor memory system comprising:

a nonvolatile semiconductor memory having;

a plurality of NAND cell units having;

a memory cell string that includes a plurality of memory cell transistors that are connected in series and capable of electrically rewriting data and storing data having two or more values represented by a threshold voltage thereof;

a first select transistor that is connected between one end of the memory cell string and a source line; and

a second select transistor that is connected between the other end of the memory cell string and a bit line,

a plurality of word lines that are connected to a gate electrode of one of the memory cell transistors in each of the NAND cell units, the plurality of word lines including a first word line that is adjacent to the first select transistor;

a first select gate line that is connected to a gate electrode of the first select transistor in each of the NAND cell units;

a second select gate line that is connected to a gate electrode of the second select transistor in each of the NAND cell units;

a row controller that selectively applies a read voltage to the word lines, the first select gate line, and the second select gate line; and

a memory controller having;

a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory;

a memory that stores writing information includes elapsed times since the latest writing in each of the NAND cell units; and

a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to the first word line;

wherein the row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating the data stored in the memory cell transistors, and

wherein the memory controller copies data stored in one of the NAND cell units when the elapsed time calculated from the writing information with respect to the one of the NAND cell units exceeds a threshold time.