THREE DIMENSIONAL NAND MEMORY

• US 20080239818A1
• Filed: 03/27/2007
• Published: 10/02/2008
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Scheuerlein, Roy
• Granted Patent: US 7,848,145 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.

Claims

1. A monolithic, three dimensional NAND string, comprising:

a first memory cell located over a second memory cell;

a select transistor;

a first word line of the first memory cell;

a second word line of the second memory cell;

a bit line;

a source line; and

a select gate line of the select transistor;

wherein;

the first and the second word lines are not parallel to the bit line; and

the first and the second word lines extend parallel to at least one of the source line and the select gate line.

2. The NAND string of claim 1, wherein:

the NAND string is formed vertically over a substrate;

the select transistor is located on a substrate or in a trench in the substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located on the select transistor and below the first device level.

3. The NAND string of claim 2, wherein:

a semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and the first word line; and

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and the second word line.

4. The NAND string of claim 3, wherein:

the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the select transistor comprises a third pillar;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar;

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar; and

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar.

5. The NAND string of claim 1, wherein:

the first and the second word lines extend perpendicular to the bit line; and

the first and the second word lines extend parallel to both the source line and the select gate line.

6. The NAND string of claim 1, wherein:

the first and the second word lines extend perpendicular to the bit line; and

the first and the second word lines extend parallel to the source line.

7. The NAND string of claim 1, wherein:

the first and the second word lines extend perpendicular to the bit line; and

the first and the second word lines extend parallel to the select gate line.

8. A monolithic, three dimensional NAND string comprising:

a first memory cell located over a second memory cell;

a first word line of the first memory cell; and

a second word line of the second memory cell;

wherein;

the first word line extends in first direction; and

the second word line extends in a second direction different from the first direction.

9. The NAND string of claim 8, wherein:

the NAND string is formed vertically over a substrate;

a select transistor is located on a substrate or in a trench in the substrate;

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located on the select transistor and below the first device level.

10. The NAND string of claim 9, wherein:

a semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and the first word line; and

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and the second word line.

11. The NAND string of claim 10, wherein:

the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the select transistor comprises a third pillar;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar;

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar; and

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar.

12. The NAND string of claim 8, wherein the first word line extends perpendicular to the second word line.

13. A NAND array, comprising:

an array of vertical NAND strings;

a plurality of word lines;

a plurality of bit lines; and

a plurality of source lines;

wherein;

the bit lines are not parallel to the word lines;

the word lines are not parallel to the source lines; and

the source lines are not parallel to the bit lines.

14. The array of claim 13, wherein:

the word lines extend perpendicular to the source lines; and

the bit lines extend diagonally with respect to the word lines and the source lines.

15. The array of claim 13, wherein:

the word lines extend perpendicular to the bit lines; and

the source lines extend diagonally with respect to the word lines and the bit lines.

16. The array of claim 13, wherein:

each vertical NAND string comprises at least two vertically arranged memory cells; and

each memory cell of each vertical NAND string has a different associated word line, bit line and source line combination that all other memory cells in the array.

17. The array of claim 16, wherein each memory cell in the array is adapted to be individually programmed.

18. A NAND array, comprising:

an array of vertical NAND strings;

a plurality of word lines;

a plurality of bit lines; and

a common source plane electrically connected each of the vertical NAND strings.

19. The array of claim 18, wherein the common source plane comprises a conductive plate.

20. The array of claim 19, wherein the conductive plate electrically contacts an active region of a select transistor of each of the vertical NAND strings.