SELF-ADAPTIVE AND SELF-CALIBRATED MULTIPLE-LEVEL NON-VOLATILE MEMORIES

• US 20080239820A1
• Filed: 03/29/2007
• Published: 10/02/2008
• Est. Priority Date: 03/29/2007
• Status: Active Grant

• Current Assignee: Pegasus Semiconductor (Beijing) Co., Ltd.
• Original Assignee: Flashsilicon, Incorporation
• Inventors: Wang, Lee
• Granted Patent: US 7,729,165 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell. As the stepped voltage applied to the gate of an NVM cell transitions from a voltage just below the threshold voltage of the NVM cell to a voltage corresponding to the threshold voltage of the NVM cell, the output current (voltage) from the NVM cell will pass the current (voltage) transition in comparison with the reference current (voltage). The current (voltage) transition can be detected and converted into the bit-word information representing the voltage level stored in the NVM cell. When the response of an NVM cell falls outside the response tolerance window into the guard-band regions, the NVM cell can be re-calibrated and the bit-word information can be saved from fading away.

Claims

1. A method of adjusting the threshold voltage of a nonvolatile memory cell having a floating gate or dielectric for receipt and storage of charge to change the threshold voltage of the cell and having a control gate for receipt of a voltage to turn on the cell when the voltage on the control gate equals or exceeds the selected threshold voltage of the cell, which comprises:

placing a selected charge corresponding to a selected threshold voltage on said floating gate or dielectric;

measuring the current from the memory cell after a charge believed to allow the cell to turn on in response to the selected threshold voltage applied to said control gate has been placed on said floating gate or dielectric and a voltage corresponding to said selected threshold voltage has been applied to said control gate;

comparing the measured current to the current that should flow when a voltage corresponding to the desired threshold voltage is applied to the control gate of the nonvolatile memory cell; and

adjusting the charge on the floating gate or dielectric to place the current within the desired range for the selected threshold voltage being applied to the control gate should the current that is measured be outside the range for current that should flow from the memory cell when the specified threshold voltage is applied to said control gate.

2. The method of claim 1 wherein the adjusting of the charge on the floating gate comprises:

placing additional charge on the floating gate to bring the output current from the nonvolatile memory cell within the tolerance band associated with the selected threshold voltage.

3. The method of claim 1 wherein the readjusting of the charge on the floating gate comprises:

reducing the charge on the floating gate to bring the output current from the nonvolatile memory cell within the tolerance band associated with the selected threshold voltage.

4. Structure for adjusting the threshold voltage of a nonvolatile memory cell having a floating gate or dielectric for receipt and storage of charge to change the threshold voltage of the cell and having a control gate for receipt of a voltage to turn on the cell when the voltage on the control gate equals or exceeds the selected threshold voltage of the cell, which comprises:

means for placing a selected charge corresponding to a selected threshold voltage on said floating gate or dielectric;

means for measuring the current from the memory cell after a charge believed to allow the cell to turn on in response to the selected threshold voltage applied to said control gate has been placed on said floating gate or dielectric and a voltage corresponding to said selected threshold voltage has been applied to said control gate;

means for comparing the measured current to the current that should flow when a voltage corresponding to the desired threshold voltage is applied to the control gate of the nonvolatile memory cell; and

means for adjusting the charge on the floating gate or dielectric to place the current within the desired range for the selected threshold voltage being applied to the control gate should the current that is measured be outside the range for current that should flow from the memory cell when the specified threshold voltage is applied to said control gate.

5. The structure of claim 4 wherein the means for adjusting the charge on the floating gate comprises:

means for placing additional charge on the floating gate or dielectric to bring the output current from the nonvolatile memory cell within the tolerance band associated with the selected threshold voltage.

6. The structure of claim 4 wherein the means for adjusting the charge on the floating gate comprises:

means for reducing the charge on the floating gate or dielectric to bring the output current from the nonvolatile memory cell within the tolerance band associated with the selected threshold voltage.

7. Structure comprising:

an array of nonvolatile memory cells, each nonvolatile memory cell having a floating gate or dielectric for receipt and storage of charge to control the threshold voltage of the cell and having a control gate for receipt of a voltage to turn on the cell when the voltage on the control gate equals or exceeds the selected threshold voltage of the cell;

means for placing any one of a selected number of charges, each charge corresponding to a selected threshold voltage, on the floating gate or dielectric associated with each memory cell in the array;

means for measuring the current from each memory cell after a charge believed to allow the cell to turn on in response to the selected threshold voltage applied to said control gate has been placed on the floating gate or dielectric associated with each memory cell and a voltage corresponding to said selected threshold voltage has been applied to the control gate;

means for comparing the measured current to the current that should flow when a voltage corresponding to the desired threshold voltage is applied to the control gate of each nonvolatile memory cell; and

means for adjusting the charge on the floating gate or dielectric of each memory cell to place the current within the desired range for the selected threshold voltage being applied to the control gate should the current that is measured be outside the range for current that should flow from the memory cell when the specified threshold voltage is applied to said control gate.

8. The structure of claim 7 wherein the means for adjusting the charge on the floating gate comprises:

means for placing additional charge on the floating gate or dielectric to bring the output current from the nonvolatile memory cell within the tolerance band associated with the selected threshold voltage.

9. The structure of claim 7 wherein the means for adjusting the charge on the floating gate comprises:

means for reducing the charge on the floating gate or dielectric to bring the output current from the nonvolatile memory cell within the tolerance band associated with the selected threshold voltage.

10. The structure of claim 7 further comprising:

means for adding to the charge on the floating gate or dielectric of one or more nonvolatile memory cells in the array should the threshold voltage of said one or more nonvolatile memory cells drop beneath a minimum desired value.

11. Structure comprising:

an array of nonvolatile memory cells arranged in M rows and N columns, each cell in the array being capable of storing any one of a plurality of different charges;

a voltage source for applying in sequence a plurality of selected voltages to row m, where m is an integer given by 1≦

m≦

M, thereby to store charges of different magnitudes on selected ones of the nonvolatile memory cells connected to said row;

logic circuitry for preventing those nonvolatile memory cells which have stored the desired charges during the application of lower voltages to row m from having the charges so stored altered as higher voltages are applied to row m; and

circuitry for restoring the desired charge on one or more memory cells associated with row m should for any reason the charge on these one or more memory cells be reduced.

12. Structure as in claim 11 further comprising:

means for causing said voltage source to initially apply voltage increments of a first magnitude to row m and once the charge stored in one or more selected nonvolatile memory cells reaches a certain magnitude, to apply voltage increments of a second magnitude to row m until the desired charge is achieved on the one or more selected nonvolatile memory cells, the second magnitude being smaller than the first magnitude.