Flash Memory with Data Refresh Triggered by Controlled Scrub Data Reads

• US 20080239851A1
• Filed: 03/28/2007
• Published: 10/02/2008
• Est. Priority Date: 03/28/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lin, Jason T.
• Granted Patent: US 7,573,773 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less than all of a block in response to a read command from a host or memory controller. The small portion is selected for the scrub read because of its greater vulnerability than other portions of the block to being disturbed as a result of the commanded partial block data read. This then determines, as the result of reading a small amount of data, whether at least some of the data in the block was disturbed by the command data read to a degree that makes it desirable to refresh the data of the block.

Claims

1. A reprogrammable non-volatile memory system, comprising:

a plurality of groups of charge storage memory cells connected in a manner that accessing less than all of the memory cells in the group can disturb the levels of charge stored in other memory cells in the group,

a controller connected with the charge storage memory cells and that operates to;

recognize when less than all the memory cells of the group have been accessed and the data stored therein has been read in response to a command,

determine whether some of the memory cells within the group have a higher degree of vulnerability to being disturbed by the commanded data read than other memory cells of the group, and, if so, identify the more vulnerable memory cells,

subsequently initiate a scrub read of data from at least some of the more vulnerable memory cells,

determine a level of quality of the scrub read data and whether it is adequate, and

if the level of quality of the read data is determined not to be adequate, refresh the data stored in the memory cells of the group.

2. The memory system of claim 1, wherein the plurality of groups of memory cells are part of an array of memory cells that have their charge storage elements connected in series in a plurality of strings, the strings being individually connectable at first and second ends thereof to respective first and second voltage sources and having control gates connected in a direction extending across the plurality of strings to individually define pages of data storage capacity, the strings further being formed into the groups of memory cells, the memory cells of individual groups being erasable concurrently.

3. The memory system of claim 1, wherein the controller further operates to:

determine the level of quality of the read data by determining a number of bit errors in the scrub read data, and

determine the level of quality of the scrub data by comparing the number of bit errors with a preset threshold.

4. The memory system of claim 1, wherein the controller further operates to:

determine a level of quality of the scrub read data by determining a first number of bit errors in at least some of the command read data and a second number of bit errors in at least some of the scrub read data, and

determine the level of quality of the scrub read data by comparing the first and second numbers of bit errors.

5. The memory system of claim 4, wherein the controller further operates to:

compare the first and second numbers of bit errors by calculating a ratio of the first and second numbers, and

thereafter comparing the ratio with a pre-defined threshold.

6. The memory system of claim 1, wherein the controller further operates to identify memory cells within the group that have a higher degree of vulnerability to being disturbed by considering the number of memory cells of the group accessed in response to the command and a sequence in which the memory cells of the group are accessed.

7. The memory system of claim 1, wherein the controller further operates to identify memory cells within the group that have a higher degree of vulnerability to being disturbed by considering physical characteristics of the memory cells in different physical locations within the group.

8. The memory system of claim 1, wherein the controller further operates to identify memory cells within the group that have a higher degree of vulnerability to being disturbed by considering patterns of data stored in the memory cells of the group.

9. The memory system of claim 1, wherein the controller further operates to identify memory cells within the group that have a higher degree of vulnerability to being disturbed by distinguishing between the memory cells that have been accessed in response to the command and other memory cells within the group.