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Test feature to improve DRAM charge retention yield

  • US 20080239852A1
  • Filed: 03/28/2007
  • Published: 10/02/2008
  • Est. Priority Date: 03/28/2007
  • Status: Abandoned Application
First Claim
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1. An apparatus comprising:

  • a first integrated circuit die; and

    a second integrated circuit die stacked together in a package, wherein the second integrated circuit die comprises a dynamic random access memory (DRAM) and circuitry to increase a refresh rate provided by a self refresh timer by a predetermined percentage.

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