Test feature to improve DRAM charge retention yield
First Claim
Patent Images
1. An apparatus comprising:
- a first integrated circuit die; and
a second integrated circuit die stacked together in a package, wherein the second integrated circuit die comprises a dynamic random access memory (DRAM) and circuitry to increase a refresh rate provided by a self refresh timer by a predetermined percentage.
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Abstract
In some embodiments, a design for test feature to improve DRAM charge retention yield is presented. In this regard, an apparatus is introduced comprising a first integrated circuit die, and a second integrated circuit die stacked together in a package, wherein the second integrated circuit die comprises a dynamic random access memory (DRAM) and circuitry to increase a refresh rate provided by a self refresh timer by a predetermined percentage. Other embodiments are also disclosed and claimed.
11 Citations
20 Claims
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1. An apparatus comprising:
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a first integrated circuit die; and a second integrated circuit die stacked together in a package, wherein the second integrated circuit die comprises a dynamic random access memory (DRAM) and circuitry to increase a refresh rate provided by a self refresh timer by a predetermined percentage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An electronic appliance comprising:
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a processor; a network controller; and a DRAM memory, wherein the DRAM memory is stacked in a package with another integrated circuit die, the system memory including circuitry to increase a refresh rate provided by a self refresh timer by a predetermined percentage. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method comprising:
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increasing the temperature of a stacked die package containing a DRAM array; increasing the refresh rate of the DRAM by a predetermined percentage; and testing the stacked die package for retention. - View Dependent Claims (17, 18, 19, 20)
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Specification