INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT

• US 20080239857A1
• Filed: 04/29/2008
• Published: 10/02/2008
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 7,761,724 B2
• Time in Patent Office: Days
• US Class Current: 365/227
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits

Claims

1. A sub-system, comprising:

an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to perform a power management operation in association with only a portion of the memory circuits.

2. The sub-system of claim 1, wherein the power management operation includes a power saving operation.

3. The sub-system of claim 2, wherein the power saving operation includes a power down operation.

4. The sub-system of claim 1, wherein the power management operation is initiated by at least one power management signal.

5. The sub-system of claim 4, wherein the at least one power management signal includes at least one of a clock enable signal, and a chip select signal.

6. The sub-system of claim 1, wherein the power management operation is initiated by at least one non-power management signal.

7. The sub-system of claim 1, wherein the power management operation is initiated based on a state of one or more of the memory circuits.

8. The sub-system of claim 7, wherein the state is selected from the group consisting of a status of the one or more of the memory circuits, a predetermined combination of commands issued to the one or more of the memory circuits, a predetermined pattern of commands issued to the one or more of the memory circuits, and a predetermined absence of commands issued to the one or more of the memory circuits.

9. The sub-system of claim 1, wherein the interface circuit is operable to simulate at least one virtual memory circuit.

10. The sub-system of claim 9, wherein the power management operation is performed in association with only a portion of the at least one virtual memory circuit.

11. The sub-system of claim 9, wherein the at least one virtual memory circuit includes a single virtual memory circuit.

12. The sub-system of claim 1, wherein the power management operation includes powering down a first portion of the memory circuits while a second portion of the memory circuits is subject to at least one command.

13. The sub-system of claim 1, wherein the interface circuit includes a circuit that is positioned on a dual in-line memory module (DIMM).

14. The sub-system of claim 1, wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).

15. The sub-system of claim 1, wherein the interface circuit and the memory circuits take the form of a stack.

16. The sub-system of claim 15, wherein the stack includes a single interface circuit.

17. The sub-system of claim 1, wherein the interface circuit includes a single register.

18. The sub-system of claim 15, wherein the stack includes a plurality of interface circuits.

19. A method, comprising:

interfacing a plurality of physical memory circuits and a system;

simulating at least one virtual memory circuit; and

performing a power management operation in association with only a portion of the at least one virtual memory circuit.

20. A system, comprising:

a plurality of physical memory circuits; and

an interface circuit in communication with the physical memory circuits and a system, the interface circuit operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit and performing a power management operation in association with only a portion of the at least one virtual memory circuit.