Receiver-Based Adaptive Equalizer with Pre-Cursor Compensation

• US 20080240223A1
• Filed: 11/22/2005
• Published: 10/02/2008
• Est. Priority Date: 11/23/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Diablo Technologies Incorporated (Rambus Inc.)
• Inventors: Badalone, Riccardo
• Granted Patent: US 8,081,677 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a wide range of communications channels. Interoperability and Bit Error Rate performance are optimized through compensation of pre-cursor inter-symbol interference, which is performed adaptively in the receiver as opposed to the transmitter.

Claims

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21. A receiver based equalization apparatus for automatically eliminating inter-symbol interference caused by a serial communication channel for a binary, Non-Return-to-Zero (NRZ), serial data stream without requiring transmit pre-equalization comprising:

i) a programmable continuous equalizer to condition said serial data stream to produce an equalized continuous output serial data stream; and

ii) control means operable to control said programmable continuous equalizer based on said incoming data stream.

22. The apparatus of claim 21 wherein said continuous equalizer comprises two distinct stages, a post-cursor compensation stage cascaded with a pre-cursor compensation stage.

23. The apparatus of claim 22 wherein said post-cursor compensation stage provides two signal paths to condition the received incoming data, one signal path being a controllable pure gain stage and the other signal path being an independently controllable pure gain stage coupled to a high-pass filter, the combined output of both supplied to said pre-cursor stage.

24. The apparatus of claim 23 wherein said pre-cursor compensation stage provides two signal paths to condition the received incoming data, one signal path being a controllable pure gain stage and the other signal path being an independently controllable pure gain stage coupled with a delay element, the combined output of both representing said continuous output serial data stream.

25. The apparatus of claim 21 wherein the control means comprising a data slicer, a positive offset monitor slicer and a negative offset monitor slicer, each slicer coupled to said output serial data stream for producing receive control parameters.

26. The apparatus of claim 21 wherein the control means comprises a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream wherein the demultiplexers provide inputs for producing said receive control parameters.

27. The apparatus of claim 21 wherein the control means comprises a storage array to store data channel bits, a positive monitor storage array to store positive monitor channel bits and a negative monitor storage array to store negative monitor channel bits, each said storage array stores bits responsive to the output of a respective slicer coupled to said continuous output serial data stream wherein said receive control parameters are determined by the bit values.

28. An equalization apparatus for automatically equalizing binary, NRZ, serial data stream over a communication channel comprising:

i) a programmable receiver to receive an incoming data stream from the communication channel including;

(a) a programmable post-cursor compensation stage to condition the received incoming serial data stream;

(b) a programmable pre-cursor compensation stage to condition the output of said post-cursor compensation stage;

(c) a programmable DFE stage to condition the output of said post-cursor compensation stage to produce an equalized output serial data stream; and

ii) a co-efficient and gain update block controller coupled to the output of said programmable receiver to produce control means to operate program said receiver based on said incoming data stream.

29. The apparatus of claim 28 wherein said post-cursor compensation stage comprises:

(a) a high-pass filter coupled to a controllable pure gain stage to condition the received incoming stream corresponding to a gain parameter G_HF;

(b) a controllable pure gain stage to condition the received incoming stream corresponding to a gain G_DC, whose output is summed with the output of said gain stage G_HF to form the output of said post-cursor stage.

30. The apparatus of claim 29 wherein said post-cursor compensation stage further comprises:

(c) a delay element coupled to a controllable pure gain stage to condition the output of said post-cursor compensation stage corresponding to a gain parameter G_AGC;

(d) a controllable pure gain stage to condition the output of said post-cursor compensation stage corresponding to a gain G_PRE, who'"'"'s output is summed with the output of said gain stage G_AGC to form the output of said pre-cursor stage.

31. The apparatus of claim 28 wherein said DFE comprises an N tap programmable non-linear decision feedback equalizer (DFE) coupled to the output of the pre-cursor compensation stage providing N symbol spaced taps, each of which can be programmed independently corresponding to a respective tap parameter C₁, C₂ . . . C_N.

32. The apparatus of claim 28 wherein said co-efficient and gain update block controller are coupled to the output of said programmable receiver to produce said gain and co-efficient parameters G_HF, G_AGC, G_PRE, G_DC, and C_-1, C₀ . . . C_N.

33. The apparatus of claim 28 wherein said co-efficient and gain update block controller further includes a data slicer, a positive offset monitor slicer and a negative offset monitor slicer each coupled to the output of said programmable receiver.

34. The apparatus of claim 28 wherein said co-efficient and gain update block controller includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream wherein the demultiplexers provide inputs for producing said gain and co-efficient parameters.

35. The apparatus of claim 28 wherein said co-efficient and gain update block controller includes a data storage array to store data channel bits, a positive monitor storage array to store positive monitor channel bits and a negative monitor storage array to store negative monitor channel bits, each said storage array stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream wherein said gain and co-efficient parameters are determined by the bit values.

36. A method for automatically updating a receiver based equalizer which has programmable pre-cursor equalizer settings and programmable post-equalizer settings comprising:

i) updating said post-cursor equalizer settings using time domain information about the polarity of a cursor b₀, the polarity of the difference between the desired amplitude of cursor b₀ and the actual receive signal amplitude, and the polarity of a first post-cursor b₁; and

ii) updating said pre-cursor equalizer settings using time domain information about the polarity of cursor b₀, the polarity of the difference between the desired amplitude of cursor b₀ and the actual receive signal amplitude, and the polarity of a first pre-cursor b_-1.

37. A method for automatically adapting a receiver based equalizer to eliminate pre-cursor inter-symbol interference caused by a serial communication channel for a binary, Non-Return-to-Zero (NRZ), serial data stream without requiring transmit pre-equalization comprising:

i) conditioning an incoming binary, NRZ, serial data stream received from the communication channel to produce an equalized output serial data stream in response to receive control parameters;

ii) recovering the serial data stream from the equalized output serial data stream;

iii) producing a symbol spaced set of error signals indicative of a difference between the equalized output serial data stream and a desired value for a given symbol; and

iv) using the error signal in combination with said recovered serial data to produce said receive control parameters.

38. The method of claim 37 further comprising the steps of:

i) over a plurality of symbol periods;

storing the recovered serial data stream in a data channel storage array;

storing the error signals produced in monitor channel storage arrays;

ii) generating the receive control parameters from selected portions of said stored recovered serial data stream and said stored error signals.

39. The method of claim 38 wherein said error signals comprise of positive offset error signals and negative offset error signals.

40. The method of claim 37 wherein said positive offset error signals are stored in a positive offset storage array and said negative offset error signals are stored in a negative offset storage array.

41. The method of claim 37 wherein said recovered serial data stream, and said error signals, are stored in separate storage arrays, are subsequently fed into a Co-Efficient and Gain Adaptation logic to generate said receive control parameters.

42. The method of claim 41 wherein said receive control parameters consist of G_HF, G_AGC, G_PRE, G_DC, and C_-1, C₀ . . . C_N.

43. The method of claim 42 wherein said Co-Efficient and Gain Adaptation logic uses a set of equations to generate updates to said receive control parameters.

44. The method of claim 41 wherein the co-efficient and gain updates generated by said Co-Efficient and Gain Adaptation logic are based on an approximation of the Least Mean Squares criterion, which is defined by C′

_x←

C_xμ

×

ε

×

Dx.

45. The method of claim 44 wherein the step size μ

is selected to be an arbitrary discrete value that can be optimized to increase the rate of convergence or improve the precision of said co-efficient or gain.

46. The method of claim 45 wherein the decimal parameter D_x refers to the analog amplitude of a given data bit x, and may be defined by a received binary data bit b_x, and wherein the polarity of the received data bit x is defined by sgn(b_x).

47. The method of claim 46 wherein if said data bit x is larger than zero and has a binary value “

1”

, then the polarity is defined as sgn(b_x)=+1.

48. The method of claim 47 wherein if said data bit x is smaller than zero and has a binary value “

0”

, said polarity is defined as sgn(b_x)=−

1.

49. The method of claim 48 wherein if said data bit x is specifically associated to the cursor then sgn(b_x)=sgn(b₀).

50. The method of any claim 46 wherein said decimal parameter ε

can be reduced to the polarity of the difference between a target signal amplitude and an actual signal amplitude for a given sampled data bit, and is defined by sgn(ε

).

51. The method of claim 50 wherein if the actual data signal is a smaller value than the target signal value, then sgn(ε

)=+1.

52. The method of claim 51 wherein if the actual data signal is larger than the desired or target signal value, then sgn(ε

)=−

1.

53. The method of claim 52 wherein if sgn(ε

) is specifically associated with a selected cursor then sgn(ε

)=sgn(ε

₀).

54. The method of claim 44 wherein said least mean squares criterion equation C′

_x←

C_x+μ

×

ε

×

Dx can be approximated to the General Gain and Update Equation C′

_x←

C_x+μ

×

sgn(ε

₀)×

sgn(b_x).

55. The method of claim 54 wherein said bit within said data channel storage array may arbitrarily be selected to represent the cursor (b₀), which will in turn provide the reference point from which to compute the sgn(b_x) parameters in said General Gain and Update Equation, and which will also provide a bit location to extract the corresponding sgn(ε

) information from said monitor channel storage arrays.

56. The method of claim 55 wherein the value of said corresponding sgn(ε

) may be determined by evaluating the error signals stored in said positive offset storage array and said negative offset storage array based on the polarity of said cursor (b₀).

57. The method of claim 56 where if said cursor (b₀) has a positive polarity, then the positive offset storage array will be used to obtain the value of sgn(ε

₀) and the information in the negative offset storage array will be discarded.

58. The method of claim 57 where if said cursor (b₀) has a negative polarity, then the negative offset storage array will be used to obtain the value of sgn(ε

₀) and the information in the negative offset storage array is discarded.

59. The method of claim 44 where the equation to update G_HF is G′

_HF←

G_HF−

μ

×

sgn(ε

₀)×

sgn(b₁).

60. The method of claim 44 where the equation to update G_DC is G′

_DC←

G_DC+μ

×

sgn(ε

₀)×

sgn(b₀).

61. The method of claim 44 where the equation to update G_AGC is G′

_AGC←

G_AGC+μ

×

sgn(ε

₀)×

sgn(b₀).

62. The method of claim 44 where the equation to update G_PRE is G′

_PRE←

G_PRE+μ

×

sgn(ε

₀)×

sgn(b_-1).

63. The method of claim 38 performed in an infinite iterative loop to obtain optimum receive control parameters.