METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY

• US 20080242028A1
• Filed: 03/27/2007
• Published: 10/02/2008
• Est. Priority Date: 03/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Scheuerlein, Roy
• Granted Patent: US 7,575,973 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell.

Claims

1. A method of making a monolithic, three dimensional NAND string comprising a first memory cell located over a second memory cell, the method comprising:

growing a semiconductor active region of second memory cell; and

epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell.

2. The method of claim 1, further comprising:

forming the second memory cell over a substrate;

epitaxially growing a first semiconductor layer on the semiconductor active region of the second memory cell;

planarizing the first semiconductor layer;

patterning the first semiconductor layer into a first semiconductor strip extending in a first direction;

forming a first insulating layer adjacent to exposed lateral sides of the first semiconductor strip;

patterning the first semiconductor strip to form a first semiconductor pillar;

forming a first charge storage dielectric located adjacent to a first exposed side of the first semiconductor pillar;

forming a first control gate adjacent to the first charge storage dielectric;

forming a second charge storage dielectric located adjacent to a second exposed side of the first semiconductor pillar; and

forming a second control gate adjacent to the second charge storage dielectric.

3. The method of claim 2, wherein:

a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell;

the first semiconductor pillar comprises the semiconductor active region of the first memory cell; and

the first semiconductor pillar comprises a first conductivity type semiconductor region located between second conductivity type semiconductor regions.

4. The method of claim 2, further comprising:

depositing a charge storage dielectric film and a control gate layer over the first semiconductor pillar;

planarizing the charge storage dielectric film and the control gate layer to expose the first semiconductor pillar and to form the first and the second charge storage dielectrics and the first and the second control gates;

partially etching the first and the second control gates;

forming a second insulating layer over the first and the second partially etched control gates; and

planarizing the second insulating layer to expose the first semiconductor pillar.

5. The method of claim 1, further comprising forming a select transistor on a substrate or in a trench in the substrate.

6. The method of claim 5, further comprising:

epitaxially growing a second semiconductor layer on a semiconductor active region of the select transistor;

planarizing the second semiconductor layer;

patterning the second semiconductor layer into a second semiconductor strip extending in a first direction;

forming a third insulating layer adjacent to exposed lateral sides of the second semiconductor strip;

patterning the second semiconductor strip to form a second semiconductor pillar;

forming a third charge storage dielectric located adjacent to a first exposed side of the second semiconductor pillar;

forming a third control gate adjacent to the third charge storage dielectric;

forming a fourth charge storage dielectric located adjacent to a second exposed side of the second semiconductor pillar; and

forming a fourth control gate adjacent to the fourth charge storage dielectric.

7. The method of claim 6, wherein:

the second semiconductor pillar comprises the semiconductor active region of the second memory cell;

the second semiconductor pillar comprises a first conductivity type semiconductor region located between second conductivity type semiconductor regions; and

the second semiconductor pillar is not aligned to a semiconductor active region of the first memory cell.

9. The method of claim 6, wherein the step of forming the select transistor comprises:

epitaxially growing a third semiconductor layer on or in a substrate;

planarizing the third semiconductor layer;

patterning the third semiconductor layer into a third semiconductor strip extending in a first direction;

forming a fourth insulating layer adjacent to exposed lateral sides of the third semiconductor strip;

patterning the third semiconductor strip to form a third semiconductor pillar;

forming a first gate dielectric located adjacent to a first exposed side of the third semiconductor pillar;

forming a first select gate adjacent to the first gate dielectric;

forming a second gate dielectric located adjacent to a second exposed side of the third semiconductor pillar; and

forming a second select gate adjacent to the second gate dielectric.

10. The method of claim 9, wherein:

the third semiconductor pillar comprises the semiconductor active region of the select transistor;

the third semiconductor pillar comprises a first conductivity type semiconductor region located between second conductivity type semiconductor regions; and

the third semiconductor pillar is not aligned to the second semiconductor pillar.

8. (canceled)

11. (canceled)

12. A method of making a monolithic, three dimensional NAND string, comprising forming a first memory cell over a second memory cell, wherein a semiconductor active region of at least the first memory cell comprises recrystallized polysilicon.

13. The method of claim 12, further comprising:

forming an amorphous silicon or polysilicon semiconductor active region of the first memory cell over the second memory cell; and

recrystallizing the amorphous silicon or polysilicon semiconductor active region of the first memory cell to form a recrystallized polysilicon semiconductor active region of the first memory cell.

14. The method of claim 13, further comprising:

forming a select transistor on a substrate or in a trench in the substrate

forming an amorphous silicon or polysilicon semiconductor active region of the second memory cell over the select transistor; and

recrystallizing the amorphous silicon or polysilicon semiconductor active region of the second memory cell to form a recrystallized polysilicon semiconductor active region of the second memory cell.

15. The method of claim 14, wherein:

the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar; and

the first pillar is not aligned with the second pillar.

16. The method of claim 15, further comprising:

forming a first charge storage dielectric located adjacent to the first conductivity type semiconductor region in the first pillar;

forming a first control gate located adjacent to the first charge storage dielectric;

forming a second charge storage dielectric located adjacent to the first conductivity type semiconductor region in the second pillar; and

forming a second control gate located adjacent to the second charge storage dielectric.

17. A method of making a monolithic, three dimensional NAND string, comprising:

forming a first memory cell over a second memory cell; and

planarizing at least one region of the NAND string.

18. The method of claim 17, further comprising:

forming the second memory cell over a substrate;

epitaxially growing a first semiconductor layer on a semiconductor active region of the second memory cell;

planarizing the first semiconductor layer;

patterning the first semiconductor layer into a first semiconductor strip extending in a first direction;

forming a first insulating layer adjacent to exposed lateral sides of the first semiconductor strip;

patterning the first semiconductor strip to form a first semiconductor pillar;

forming a first charge storage dielectric located adjacent to a first exposed side of the first semiconductor pillar;

forming a first control gate adjacent to the first charge storage dielectric;

forming a second charge storage dielectric located adjacent to a second exposed side of the first semiconductor pillar; and

forming a second control gate adjacent to the second charge storage dielectric.

19. The method of claim 18, wherein:

the first semiconductor pillar comprises a semiconductor active region of the first memory cell; and

the first semiconductor pillar comprises a first conductivity type semiconductor region located between second conductivity type semiconductor regions.

20. The method of claim 19, further comprising:

depositing a charge storage dielectric film and a control gate layer over the first semiconductor pillar;

planarizing the charge storage dielectric film and the control gate layer to expose the first semiconductor pillar and to form the first and the second charge storage dielectrics and the first and the second control gates;

partially etching the first and the second control gates;

forming a second insulating layer over the first and the second partially etched control gates; and

planarizing the second insulating layer to expose the first semiconductor pillar.

21. The method of claim 17, wherein the step of planarizing comprises planarizing by chemical mechanical polishing.

22. A method of making a monolithic, three dimensional array of semiconductor memory devices, comprising:

forming an array of select transistors in a first device level using only two photolithography steps; and

forming an array of memory cells in a second device level different from the first device level using only two additional photolithography steps.

23. The method of claim 22, further comprising:

forming a first photoresist layer over a first semiconductor layer;

exposing the first photoresist layer through a first photolithographic mask;

patterning the first semiconductor layer into a plurality of first strips;

forming a second photoresist layer over the plurality of first strips;

exposing the second photoresist layer through a second photolithographic mask;

patterning the plurality of first strips into a plurality of semiconductor pillar active regions of the array of select transistors;

forming a second semiconductor layer over the array of select transistors;

forming a third photoresist layer over the second semiconductor layer;

exposing the third photoresist layer through a third photolithographic mask;

patterning the second semiconductor layer into a plurality of second strips;

forming a fourth photoresist layer over the plurality of second strips;

exposing the fourth photoresist layer through a fourth photolithographic mask; and

patterning the plurality of second strips into a plurality of semiconductor pillar active regions of the array of memory cells in the second device level.

24. The method of claim 23, further comprising:

forming a third semiconductor layer over the array of memory cells in the second device level;

forming a fifth photoresist layer over the third semiconductor layer;

exposing the fifth photoresist layer through a fifth photolithographic mask;

patterning the third semiconductor layer into a plurality of third strips;

forming a sixth photoresist layer over the plurality of third strips;

exposing the sixth photoresist layer through a sixth photolithographic mask;

patterning the plurality of third strips into a plurality of semiconductor pillar active regions of an array of memory cells in a third device level.

25. The method of claim 22, wherein the array of semiconductor memory devices comprises an array of vertical NAND strings.

26. A method of making a monolithic, three dimensional NAND device comprising a first NAND device level located over a second NAND device level, the method comprising:

growing a semiconductor layer of the second NAND device level; and

epitaxially growing a semiconductor layer of the first NAND device level over the semiconductor layer of the second NAND device level in a different growth step from the step of growing the semiconductor layer of second NAND device level.

27. The method of claim 26, wherein:

the semiconductor layer the first NAND device level comprises a single crystal silicon active region; and

the semiconductor layer the second NAND device level comprises a single crystal silicon active region.