Method for implementing diffusion barrier in 3D memory

• US 20080242080A1
• Filed: 03/30/2007
• Published: 10/02/2008
• Est. Priority Date: 03/30/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Tanaka, Yoichiro
• Granted Patent: US 7,629,253 B2
• Time in Patent Office: Days
• US Class Current: 438/653
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array.

Claims

1. A method of forming a memory cell, comprising:

filling a trench in a first dielectric with a first conductor;

recessing the first conductor in the first dielectric;

filling the recess with a first diffusion barrier;

forming a pillar over the first diffusion barrier; and

forming a second conductor over the pillar,

the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell.

2. The method of claim 1, forming the pillar comprising:

forming a layer of semiconductor material over the first diffusion barrier and the first dielectric;

forming a layer of antifuse material over the layer of semiconductor material; and

patterning the layer of antifuse material and layer of semiconductor material, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell.

3. The method of claim 2, forming the pillar comprising:

forming a layer of hardmask material over the layer of antifuse material; and

patterning the layer of hardmask material, layer of antifuse material and layer of semiconductor material.

4. The method of claim 3, the conductors comprising copper.

5. The method of claim 4, comprising:

lining the trench with the first diffusion barrier such that the first conductor is surrounded by the first diffusion barrier.

6. The method of claim 5, forming the pillar comprising:

forming a layer of second diffusion barrier material over the layer of antifuse material;

forming a layer of hardmask material over the layer of second diffusion barrier material; and

patterning the layer of hardmask material, layer of second diffusion barrier material, layer of antifuse material and layer of semiconductor material.

7. The method of claim 6, comprising:

forming a third diffusion barrier over the first diffusion barrier in the recess.

8. The method of claim 7, comprising:

lining the trench with the third diffusion barrier such that the first conductor is surrounded by the first diffusion barrier with the first diffusion barrier surrounded by the third diffusion barrier.

9. The method of claim 8, the pillar not comprising germanium or a germanium alloy.

10. A method of forming a memory cell, comprising:

filling a trench in a first dielectric with a first conductor;

forming a pillar over the first conductor; and

forming a second conductor over the pillar,

the pillar not comprising germanium or a germanium alloy, the pillar having a first electrical conductivity before a program voltage is applied to the cell and a second electrical conductivity after a program voltage is applied to the cell.

11. The method of claim 10, comprising:

recessing the first conductor in the first dielectric; and

filling the recess with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier.

12. The method of claim 11, forming the pillar comprising:

forming a layer of semiconductor material over the first diffusion barrier and the first dielectric;

forming a layer of antifuse material over the layer of semiconductor material; and

patterning the layer of antifuse material and layer of semiconductor material, the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell.

13. The method of claim 12, forming the pillar comprising:

forming a layer of hardmask material over the layer of antifuse material; and

patterning the layer of hardmask material, layer of antifuse material and layer of semiconductor material.

14. The method of claim 13, the conductors comprising copper.

15. The method of claim 14, comprising:

lining the trench with the first diffusion barrier such that the first conductor is surrounded by the first diffusion barrier.

16. The method of claim 15, forming the pillar comprising:

forming a layer of second diffusion barrier material over the layer of antifuse material;

forming a layer of hardmask material over the layer of second diffusion barrier material; and

patterning the layer of hardmask material, layer of second diffusion barrier material, layer of antifuse material and layer of semiconductor material.

17. The method of claim 16, comprising:

forming a third diffusion barrier over the first diffusion barrier in the recess.

18. The method of claim 17, comprising:

lining the trench with the third diffusion barrier such that the first conductor is surrounded by the first diffusion barrier with the first diffusion barrier surrounded by the third diffusion barrier.

19. A method of forming a memory cell, comprising:

filling a trench in a first dielectric with a first copper conductor;

forming a layer of semiconductor material over the first conductor and the first dielectric;

forming a layer of antifuse material over the layer of semiconductor material;

forming a layer of hardmask material over the layer of antifuse material;

patterning the layer of hardmask material, layer of antifuse material and layer of semiconductor material to form a pillar; and

forming a second copper conductor over the pillar,

the antifuse being in a first conductivity state before a program voltage is applied to the cell and a second conductivity state after a program voltage is applied to the cell.

20. The method of claim 19, comprising:

recessing the first conductor in the first dielectric; and

filling the recess with a first diffusion barrier such that the pillar interfaces with the first diffusion barrier.

21. The method of claim 20, comprising:

lining the trench with the first diffusion barrier such that the first conductor is surrounded by the first diffusion barrier.

22. The method of claim 21, comprising:

forming a layer of second diffusion barrier material over the layer of antifuse material;

forming a layer of hardmask material over the layer of second diffusion barrier material; and

patterning the layer of hardmask material, layer of second diffusion barrier material, layer of antifuse material and layer of semiconductor material to form the pillar.

23. The method of claim 22, comprising:

forming a third diffusion barrier over the first diffusion barrier in the recess.

24. The method of claim 23, comprising:

lining the trench with the third diffusion barrier such that the first conductor is surrounded by the first diffusion barrier with the first diffusion barrier surrounded by the third diffusion barrier.

25. The method of claim 24, the semiconductor not comprising germanium or a germanium alloy.