PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING
First Claim
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1. A interleaving module comprising:
- a first memory to store data packets in association with a function identifier and to store a data stream in association with a stream identifier;
a direct memory access (DMA) engine coupled to the first memory;
a second memory coupled to the DMA engine, the second memory to store a buffer pointer; and
a microcode module coupled to the DMA engine, the microcode to control a data path and an address generator.
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Abstract
Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.
30 Citations
30 Claims
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1. A interleaving module comprising:
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a first memory to store data packets in association with a function identifier and to store a data stream in association with a stream identifier; a direct memory access (DMA) engine coupled to the first memory; a second memory coupled to the DMA engine, the second memory to store a buffer pointer; and a microcode module coupled to the DMA engine, the microcode to control a data path and an address generator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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storing streams of data in association with a prefixed stream identifier; interleaving the steams of data using a direct memory access (DMA) engine operating according to a microcode; and packetizing the steams of data after interleaving. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A machine-readable medium having machine readable instructions for causing one or more interleaving modules to:
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store streaming data in association with a stream identifier; interleave the streaming data using timestamps; pass a memory pointer between memory access engine modules pointing to processed data generated from the streaming data; and schedule movement of data packets in and out of a switch matrix using the timestamps. - View Dependent Claims (20, 21, 22, 23)
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24. A system comprising:
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a central processing unit; and an interleaving module coupled to the central processing unit, the interleaving module to process signals associated with one or more wireless and broadband standards, the interleaving module comprising; a first memory to store input data in association a stream identification tag; a direct memory access (DMA) engine coupled to the first memory, the DMA engine coupled to a microcode module to control a data path; and a second memory coupled to the DMA engine to receive a pointer associated with a data interleaving process - View Dependent Claims (25, 26, 27, 28, 29, 30)
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Specification