PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING

• US 20080244115A1
• Filed: 10/30/2007
• Published: 10/02/2008
• Est. Priority Date: 03/31/2007
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hoffman, Jeffrey D.
• Application Number:
  US11/929,557
• Publication Number:
  US 20080244115A1
• Time in Patent Office: Days
• US Class Current: 710/25
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/235 Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
• CPC Class Codes: H03M 13/6519 Support of multiple transmission or communication standards
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 88/06 adapted for operation in multiple networks or having at least two operational modes, e.g. multi-mode terminals
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.

Claims

1. A coding element comprising:

a memory to store data in association with a stream identification tag and a function identification tag;

a direct memory access (DMA) engine coupled to the memory, the access engine including a microcode module; and

a linear feedback shift register coupled to the DMA engine, the linear feedback shift register to operate on the data using an algorithm associated with the function identification tag.

2. The coding element of claim 1, wherein the DMA engine includes at least one of an input DMA engine module, an output DMA engine module, and a local DMA engine module.

3. The coding element of claim 1, wherein the microcode module includes a prologue section, a dialog section, and an epilogue section.

4. The coding element of claim 1, wherein the DMA engine includes a header module to packetize output data.

5. The coding element of claim 1, wherein the DMA engine is to generate interrupt signals for interaction with a processor.

6. The coding element of claim 1, wherein the memory is configured to operate as a scratchpad.

7. The coding element of claim 1, wherein the linear feedback shift register is configurable in at least one of a polynomial length and a polynomial coefficient.

8. The coding element of claim 1, wherein the linear feedback shift register is to process signals associated with a plurality of wireless and broadband standards.

9. The coding element of claim 1, wherein the linear feedback shift register is for at least one of a cyclic redundancy check, encryption, decryption, scrambling, and convolutional coding.

10. The coding element of claim 1, wherein the linear feedback shift register is coupled to a context memory to save a current linear shift feedback register state for a first data stream while processing a second data stream.

11. A method comprising:

storing a data stream in association with a prefixed stream identifier;

controlling a process flow for the data stream between a memory and a linear feedback shift register using a microcode; and

processing the data stream using the linear feedback shift register and a prefixed function identifier.

12. The method of claim 11, further comprising processing timestamps associated with the data stream for scheduling movement of data packets in and out of a switch matrix.

13. The method of claim 12, where processing includes processing timestamps for removing jitter and reducing latency.

14. The method of claim 11, wherein processing includes generating a cyclic redundancy check.

15. The method of claim 11, wherein processing includes encrypting, decrypting, scrambling, and convolutional coding.

16. The method of claim 11, wherein storing includes storing a data stream associated with signals formatted to a plurality of different wireless and broadband standards.

17. The method of claim 11, wherein processing includes pseudo-simultaneously processing the data stream.

18. The method of claim 11, wherein controlling includes generating interrupt signal using a direct memory access engine.

19. The method of claim 11, wherein processing includes storing intermediate values generated by the linear feedback shift register.

20. A machine-readable medium having machine readable instructions for causing one or more coding elements to:

store data sets in association with either a stream identifier or a function identifier;

control routing of the data sets between a memory and a linear feedback shift register using a microcode;

process the data sets using the linear feedback shift register; and

process timestamps for the data sets associated with the stream identifier for scheduling movement of data packets in and out of a switch matrix.

21. The machine-readable medium of claim 20, wherein to process the data sets includes to generate a cyclic redundancy check.

22. The machine-readable medium of claim 20, wherein to process the data sets includes to perform at least one of encryption, decryption, scrambling, and convolutional coding.

23. The machine-readable medium of claim 20, wherein to control includes to pseudo-simultaneously control routing of the data sets using a direct memory access engine.

24. The machine-readable medium of claim 20, wherein the machine readable instructions further comprise instructions to generate data packets using a header table.

25. A system comprising:

a central processing unit; and

a coding element coupled to the central processing unit, the coding element to process signals associated with one or more wireless and broadband standards, the coding element comprising;

a memory to store data in association with a stream identification tag and a function identification tag;

a direct memory access (DMA) engine coupled to the memory, the DMA engine including a microcode module; and

a linear feedback shift register coupled to the DMA engine, the linear feedback shift register to operate on the data associated the stream identification tag.

26. The system of claim 25, wherein the microcode module includes at least one of a prologue section, a dialog section, and an epilog section.

27. The system of claim 25, wherein the central processing unit is coupled to either an auto-composing transceiver or an auto-composing receiver.

28. The system of claim 25, wherein the DMA engine includes a local DMA engine module.

29. The system of claim 28, wherein the coding element is to perform at least one of a cyclic redundancy check, an encryption, a decryption, a scrambling and a convolutional coding.

30. The system of claim 25, wherein coding element is to use timestamps to remove time jitter or reduce latency.