Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller

• US 20080244135A1
• Filed: 05/01/2006
• Published: 10/02/2008
• Est. Priority Date: 05/04/2005
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Radulescu, Andrei, Goossens, Kees Gerard Willem, Steenhof, Frits Anthonie, Akesson, Kjell Benny
• Application Number:
  US11/913,660
• Publication Number:
  US 20080244135A1
• Time in Patent Office: Days
• US Class Current: 710/241
• CPC Class Codes: G06F 13/1626 by reordering requests

Abstract

In the method for controlling access of a plurality of requestors to a shared memory, the following steps are repeated for successive time-windows: receiving access requests from various requestors (S1), determining a type of access requested by the requests, comparing the requested access type with an access type authorized for a respective time-window according to a back-end schedule, generating a first selection of the incoming requests which have the prescribed access type for the relevant time-window, dynamically selecting one of the requests from the first selection.

Claims

1. A method for controlling access of a plurality of requesters to a shared memory during a time window comprising:

receiving access requests from various requestors;

determining a type of access requested by the requests;

comparing the requested access type with an access type authorized for said time-window according to a back-end schedule;

generating a first selection of the incoming requests which have the prescribed access type for the said time-window;

dynamically selecting one of the requests from the first selection.

2. A memory controller for controlling access of a plurality of requesters to a shared memory, the memory controller comprising, an input for receiving requests for access to the memory from the plurality of requestors, an arbitrator for dynamically granting one of the requests in accordance with a predetermined back end schedule comprising a sequence of basic groups.

3. A memory controller according to claim 2, wherein the memory has at least two memory banks, and wherein the back end schedule provides separate time windows for access of the different banks in an interleaved fashion.

4. A memory controller according to claim 2, wherein the back end schedule is fixed.

5. A memory controller according to claim 2, comprising a facility for allowing a user to program the back end schedule.

6. A memory controller according to claim 2, wherein the scheduler has a facility for dynamically updating the back end schedule.

7. (canceled)