×

PROCESSOR CHIP ARCITECTURE HAVING INTEGRATED HIGH-SPEED PACKET SWITCHED SERIAL INTERFACE

  • US 20080244150A1
  • Filed: 02/04/2008
  • Published: 10/02/2008
  • Est. Priority Date: 02/02/2007
  • Status: Active Grant
First Claim
Patent Images

1. An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:

  • at least one processor core; and

    at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide a high-speed packet switched serial interface to the at least processor core,wherein the at least one processor core and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible,such that the high-speed packet switched serial interface transfers data, address and control information required to fetch and write data from and to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol.

View all claims
  • 5 Assignments
Timeline View
Assignment View
    ×
    ×