PROCESSOR CHIP ARCITECTURE HAVING INTEGRATED HIGH-SPEED PACKET SWITCHED SERIAL INTERFACE
First Claim
1. An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:
- at least one processor core; and
at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide a high-speed packet switched serial interface to the at least processor core,wherein the at least one processor core and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible,such that the high-speed packet switched serial interface transfers data, address and control information required to fetch and write data from and to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol.
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Accused Products
Abstract
A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.
37 Citations
19 Claims
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1. An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:
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at least one processor core; and at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide a high-speed packet switched serial interface to the at least processor core, wherein the at least one processor core and the at least one packet processor are co-located on a semiconductor die package having at least one external port over which the high-speed packet switched serial interface is accessible, such that the high-speed packet switched serial interface transfers data, address and control information required to fetch and write data from and to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of implementing a computing and communication chip architecture for integrated circuitry, comprising:
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providing a semiconductor die package having co-located thereon at least one processor core with at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide a high-speed packet switched serial interface to the at least processor core; and utilizing the high-speed packet switched serial interface to transfer data, address and control information required to fetch and write data from and to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol. - View Dependent Claims (10, 11, 12, 13)
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14. A computer readable media having recorded thereon instructions for implementing a computing and communication chip architecture for integrated circuitry on a semiconductor die package, comprising:
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instructions defining at least one processor core co-located on the semiconductor die package with at least one packet processor uniquely associated with each of the at least one processor core, the at least one packet processor adapted to provide a high-speed packet switched serial interface to the at least processor core; and instructions defining at least one external port to the semiconductor die package over which the high-speed packet switched serial interface is accessible, such that the high-speed packet switched serial interface transfers data, address and control information required to fetch and write data from and to an external memory device configured as a system main memory for the at least one processor core using a serial packetized protocol. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification