Circuit for Compression and Storage of Circuit Diagnosis Data

• US 20080244346A1
• Filed: 05/21/2008
• Published: 10/02/2008
• Est. Priority Date: 06/17/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Beck, Matthias, Goessel, Michael, Rzeha, Jan, Muhmenthaler, Peter, Poehl, Frank
• Granted Patent: US 7,716,547 B2
• Time in Patent Office: Days
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921

Abstract

A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.

Claims

1. A circuit arrangement, comprising:

an electronic circuit to be tested and/or diagnosed comprising a plurality of circuit inputs for receiving input data and a plurality of circuit outputs for supplying output data;

a compactor comprising;

test data inputs connected to the circuit outputs, test comparison inputs, and test data outputs; and

a memory device disposed on a semiconductor chip with the electronic circuit and the compactor, the memory device being configured to receive data supplied at the test data outputs of the compactor.

2. The circuit arrangement of claim 1, wherein the compactor further comprises:

a plurality of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that the data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code; and

compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.

3. The circuit arrangement of claim 2, wherein the compensation XOR gates are arranged downstream from the H matrix XOR gates and upstream of the test data outputs in a signal flow direction.

4. The circuit arrangement of claim 2, wherein the compensation XOR gates are arranged upstream of the H matrix XOR gates and downstream from the test data inputs in a signal flow direction.

5. The circuit arrangement of claim 2, wherein the compensation XOR gates are arranged between the H matrix XOR gates, the test data outputs, and the test data inputs in a signal flow direction such that a predetermined compression rate of a test result and a predetermined error indication probability for an error situation result.

6. The circuit arrangement of claim 2, wherein at least one masking device is arranged immediately downstream from a compensation XOR gate.

7. The circuit arrangement of claim 6, wherein an input of at least one compensation XOR gate and an input of at least one masking device are connected to each another so as to produce a common control.

8. The circuit arrangement of claim 1, further comprising at least one error indication circuit whose inputs are connected to signal paths between the test data inputs and test data outputs, the error indication circuit generating an error indication signal.

9. The circuit arrangement of claim 8, wherein the error indication circuit comprises an OR gate.

10. The circuit arrangement of claim 8, wherein the error indication circuit comprises a combinational switching mechanism that emits an error signal in response to a number of error signals exceeding a predetermined threshold value.

11. The circuit arrangement of claim 8, further comprising a masking device arranged upstream of one or more test data inputs for applying a predetermined masking signal.

12. The circuit arrangement of claim 11, wherein the masking device is an OR gate, an AND gate, a NOR gate, or a NAND gate.

13. The circuit arrangement of claim 8, further comprising one or more masking devices respectively arranged upstream of one or more of the test data outputs of the compactor, the one or more masking devices being configured to apply a predetermined masking signal.

14. The circuit arrangement of claim 8, further comprising a first circuit including XOR gates, AND gates, and multiplexers for processing X values, wherein:

the test data outputs of the compactor provide intermediate syndrome values and are respectively connected to inputs of the XOR gates of the first circuit and to inputs of the multiplexers;

the outputs of the XOR gates of the first circuit are connected to inputs of the multiplexers;

the error indication signal is supplied to inputs of the AND gates, and a plurality of correction values are respectively applied to inputs of the AND gates; and

outputs of the AND gates are respectively applied to inputs of the XOR gates of the first circuit.

15. The circuit arrangement of claim 14, further comprising a second circuit including at least one OR gate and at least one further AND gate which provide an error indication when an X value occurs, wherein outputs of the XOR gates of the first circuit are supplied to inputs of the at least one OR gate, which generates an error signal.

16. The circuit arrangement of claim 1, wherein at least some of the test data inputs of the compactor are connected to circuit outputs of the electronic circuit, which are outputs of scan paths.