NON-VOLATILE MEMORY WITH GUIDED SIMULATED ANNEALING ERROR CORRECTION CONTROL

• US 20080244367A1
• Filed: 03/31/2007
• Published: 10/02/2008
• Est. Priority Date: 03/31/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Chin, Henry, Mokhlesi, Nima
• Granted Patent: US 7,975,209 B2
• Time in Patent Office: Days
• US Class Current: 714/800
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes

Abstract

Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility during the iterative decoding that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

Claims

18. A non-volatile memory system, comprising:

a set of non-volatile storage elements; and

managing circuitry in communication with the set of storage elements, the managing circuitry reads the set of storage elements by;

detecting state information for the set of non-volatile storage elements;

providing one or more code words based on the state information;

detecting one or more errors associated with the one or more code words;

performing a number of iterations of decoding for said one or more code words, wherein decoding includes assigning reliability metrics to bits of the one or more code words and adjusting the reliability metrics for subsequent decoding iterations in an attempt to decrease said one or more errors; and

after the number of iterations, simulating annealing for the one or more code words, wherein simulating annealing includes providing at least a pseudo-random adjustment to one or more of said reliability metrics.

19. A non-volatile memory system, comprising:

a set of non-volatile storage elements;

managing circuitry in communication with the set of non-volatile storage elements, the managing circuitry performs one or more read operations that include;

detecting state information for the set of non-volatile storage elements;

providing one or more code words based on the state information;

detecting one or more errors associated with the one or more code words; and

performing a number of iterations of decoding for the one or more code words, wherein decoding includes assigning reliability metrics to bits of the one or more code words and adjusting the reliability metrics for subsequent decoding iterations in an attempt to decrease the one or more errors, wherein at least one the iterations includes guiding an adjustment to at least one reliability metric based on a predetermined characterization of the set of non-volatile storage elements.