SYSTEM AND METHOD OF CUSTOMIZING AN EXISTING PROCESSOR DESIGN HAVING AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE WITH INSTRUCTION EXTENSIONS

• US 20080244471A1
• Filed: 06/09/2008
• Published: 10/02/2008
• Est. Priority Date: 02/05/1999
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Killian, Earl A., Wang, Albert Ren-Rui, Dixit, Ashish B., Wilson, Robert P., Rowen, Christopher, Maydan, Dror Eliezer, Gonzalez, Ricardo E., Ruttenberg, John C., Lam, Monica, Lichtenstein, Walter D.
• Granted Patent: US 8,875,068 B2
• Time in Patent Office: Days
• US Class Current: 716/1
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 8/20 Software design
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 8/53 Decompilation; Disassembly

Abstract

An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Claims

1. (canceled)

2. A computer readable medium storing software code for customizing an existing processor design having an existing processor instruction set architecture (ISA) with instruction extensions to supplement the existing processor ISA, the computer readable medium storing:

code for receiving an instruction extension description for a new instruction from a user; and

code for modifying circuitry of the existing processor design to support the new instruction based on the received instruction extension description.

3. The computer readable medium of claim 2, wherein the code for modifying circuitry of the existing processor design includes code for modifying the circuitry of the existing processor design without receiving instruction descriptions for the existing processor ISA from the user.

4. The computer readable medium of claim 2, wherein the code for modifying circuitry of the existing processor design includes code for generating a processor design data containing an RTL representation of the customized processor design having the existing processor ISA and the new instruction.

5. The computer readable medium of claim 2, wherein the code for receiving an instruction extension description includes code for receiving a description of an instruction opcode.

6. The computer readable medium of claim 2, wherein the code for receiving an instruction extension description includes code for receiving a description of at least one instruction operand.

7. The computer readable medium of claim 2, wherein the code for receiving an instruction extension description includes code for receiving a description of instruction semantics containing a hardware description language that describes combinatorial circuits corresponding to the new instruction.

8. The computer readable medium of claim 2, wherein the code for receiving an instruction extension description includes code for receiving an instruction class to which the new instruction belongs.

9. The computer readable medium of claim 2, wherein the code for receiving an instruction extension description includes code for receiving a description of at least one instruction field.

10. The computer readable medium of claim 2, wherein the code for receiving an instruction extension description includes code for receiving a description of a constant table.

11. A method of customizing an existing processor design having an existing processor instruction set architecture (ISA) with instruction extensions to supplement the existing processor ISA, the method comprising:

receiving an instruction extension description for a new instruction from a user; and

modifying, by a processor build software, circuitry of the existing processor design to support the new instruction based on the received instruction extension description.

12. The method of claim 11, wherein the step of modifying circuitry of the existing processor design includes modifying the circuitry of the existing processor design without receiving instruction descriptions for the existing processor ISA from the user.

13. The method of claim 11, wherein the step of modifying circuitry of the existing processor design includes generating a processor design data containing an RTL representation of the customized processor design having the existing processor ISA and the new instruction.

14. The method of claim 11, wherein the step of receiving an instruction extension description includes receiving a description of an instruction opcode.

15. The method of claim 11, wherein the step of receiving an instruction extension description includes receiving a description of at least one instruction operand.

16. The method of claim 11, wherein the step of receiving an instruction extension description includes receiving a description of instruction semantics containing a hardware description language that describes combinatorial circuits corresponding to the new instruction.

17. The method of claim 11, wherein the step of receiving an instruction extension description includes receiving an instruction class to which the new instruction belongs.

18. The method of claim 11, wherein the step of receiving an instruction extension description includes receiving a description of at least one instruction field.

19. The method of claim 11, wherein the step of receiving an instruction extension description includes receiving a description of a constant table.