IC CARD

• US 20080245878A1
• Filed: 03/18/2008
• Published: 10/09/2008
• Est. Priority Date: 04/05/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Iida, Tetsuya, Kurakata, Shigeo, Asari, Shinsuke, SHIOTA, Shigemasa, Fukasawa, Shinichi
• Application Number:
  US12/050,926
• Publication Number:
  US 20080245878A1
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07 with integrated circuit chips
• CPC Class Codes: G06K 19/07732 the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks housings for electrical equipment in general, see H05K5/02

Abstract

Disclosed is a semiconductor device including built-in interface circuits whose operations are selected in response to initialization operation from a host apparatus coupled thereto. In the semiconductor device, a first synchronous interface circuit and a second asynchronous interface circuit using differential signals, share the external terminals of the differential signals (the external differential signal terminals). For example, the semiconductor device adopts an MMC interface circuit as the first interface circuit and a USB interface circuit as the second interface circuit, while keeping the IC card interface function. The semiconductor device selects operations of the adopted interface circuits exclusively. One selection method is to enable an interface operation of the first interface circuit, upon detection of a plurality of edge changes in a clock input from an external clock terminal, which is for initializing the first interface circuit when power supply to the semiconductor device is started.

Claims

1. A semiconductor device comprising:

a first interface circuit for interfacing signals using second external terminals, upon receiving a clock input from a first external terminal;

a second interface circuit for interfacing differential signals using the second external terminals, without receiving a clock input from the outside; and

a selection control circuit for detecting an input of a plurality of first clocks from the first external signal at the start of power supply, and outputting an activation signal of a first instruction signal to enable the interface operation of the first interface circuit.

2. The semiconductor device according to claim 1,

wherein the semiconductor device receives a command from the second external terminal when a plurality of second clocks are input to the first external terminal at the start of power supply, and

wherein the number of first clocks is a clock number in the midstream of reaching the number of second clocks.

3. The semiconductor device according to claim 2,

wherein, in response to the start of power supply, the selection control circuit initially disables the interface operation of the first interface circuit due to inactivation of the first instruction signal, and initially enables the interface operation of the second interface circuit due to activation of a second instruction signal output from the selection control circuit, and upon detection of the input of the first clocks, the selection control circuit disables the interface operation of the second interface circuit due to inactivation of the second instruction signal, and enables the interface operation of the first interface circuit due to activation of the first instruction signal.

4. The semiconductor device according to claim 3,

wherein the first interface circuit determines that the activation signal of the first instruction signal is in a defined state at a predetermined timing after the start of power supply, and outputs a first mask signal for fixing the state of the second instruction signal to a disable instruction state, and

wherein the second interface circuit determines that the activation signal of the second instruction signal is in a defined state at a predetermined timing after the start of power supply, and outputs a second mask signal for fixing the state of the first instruction signal to a disable instruction state.

5. The semiconductor device according to claim 4,

wherein, when the interface operation of the first interface circuit is enabled, the first interface circuit releases the disable instruction state to the second instruction signal in response to reset instructions supplied to the second external terminals, and

wherein, when the interface operation of the second interface circuit is enabled, the second interface circuit releases the disable instruction state to the first instruction signal in response to reset instructions supplied to the second external terminals.

6. The semiconductor device according to claim 4, further comprising a latch circuit for latching detection results obtained by a plurality of times of detecting the input of the clocks,

wherein the latch circuit performs latch operation due to the disable instruction state to the second instruction signal by the first mask signal, or due to the disable instruction state to the first instruction signal by the second mask signal.

7. The semiconductor device according to claim 6,

wherein, when the interface operations of the first and second interface circuits are enabled, the interface circuits initialize the latch circuit to a through state in response to the reset instructions supplied to the second external terminals.

8. The semiconductor device according to claim 1, further comprising:

a memory controller coupled to the first and second interface circuits by an internal bus; and

a non-volatile memory coupled to the memory controller.

9. The semiconductor device according to claim 8, further comprising a microcomputer coupled to third external terminals.

10. The semiconductor device according to claim 9,

wherein the first external terminal is defined as a clock terminal,

wherein the second external terminals are defined as a data terminal and a command terminal when used in the interface operation of the first interface circuit, and defined as a non-inverted data terminal and an inverted data terminal when used in the interface operation of the second interface circuit, and

wherein the third external terminals are defined as a reset terminal, a clock terminal, and an input/output terminal.

11. The semiconductor device according to claim 1,

wherein the first interface circuit is an MMC interface circuit or an SD card interface circuit, and

wherein the second interface circuit is a USB interface circuit.

29. The semiconductor device according to claim 2, further comprising:

a memory controller coupled to the first and second interface circuits by an internal bus; and

a non-volatile memory coupled to the memory controller.

30. The semiconductor device according to claim 29, further comprising a microcomputer coupled to third external terminals.

31. The semiconductor device according to claim 30,

wherein the first external terminal is defined as a clock terminal,

wherein the second external terminals are defined as a data terminal and a command terminal when used in the interface operation of the first interface circuit, and defined as a non-inverted data terminal and an inverted data terminal when used in the interface operation of the second interface circuit, and

wherein the third external terminals are defined as a reset terminal, a clock terminal, and an input/output terminal.

32. The semiconductor device according to claim 2,

wherein the first interface circuit is an MMC interface circuit or an SD card interface circuit, and

wherein the second interface circuit is a USB interface circuit.

12. A semiconductor device comprising:

a first interface circuit for interfacing signals using a pair of second external terminals, upon receiving a clock input from a first external terminal;

a second interface circuit for interfacing differential signals using the second external terminals, without receiving a clock input from the outside;

a first high-resistance DC circuit for initializing the second external terminals to a first level in response to the start of power supply;

a selection control circuit for enabling an interface operation of the second interface circuit by a first instruction signal, upon detection of a second level supplied to the initialized second external terminals; and

a second high-resistance DC circuit for changing the one of the second external terminals to a first level in response to the detection of the second level by the selection control circuit, so that the coupling of the second interface circuit can be recognized from the outside of the second external terminal.

13. The semiconductor device according to claim 12,

wherein, in response to the start of power supply, the selection control circuit initially disables the interface operation of the second interface circuit by the first instruction signal, and initially enables the interface operation of the first interface circuit by a second instruction signal output from the selection control circuit, and upon detection of the second level, the selection control circuit disables the interface operation of the first interface circuit, and enables the interface operation of the second interface circuit.

14. The semiconductor device according to claim 13,

wherein the first interface circuit determines that the instruction state by the second instruction signal is a defined state at a predetermined timing after the start of power supply, and outputs a first mask signal for fixing the state of the first instruction signal to a disable instruction state, and

wherein the second interface circuit determines that the instruction state by the first instruction signal is a defined state at a predetermined timing after the start of power supply, and outputs a second mask signal for fixing the state of the second instruction signal to a disable instruction state.

15. The semiconductor device according to claim 14,

wherein, when the interface operation of the first interface circuit is enabled, the first interface circuit releases the disable instruction state to the first instruction signal in response to reset instructions supplied to the second external terminals, and

wherein, when the interface operation of the second interface circuit is enabled, the second interface circuit releases the disable instruction state to the second instruction signal in response to reset instructions supplied to the second external terminals.

16. The semiconductor device according to claim 14, further comprising a latch circuit for latching the detection result obtained by detecting the second level, and

wherein the latch circuit performs latch operation due to the disable instruction state to the first instruction signal by the first mask signal, or due to the disable instruction state to the second instruction signal by the second mask signal.

17. The semiconductor device according to claim 15,

wherein, when the interface operations of the first and second interface circuits are enabled, the interface circuits initialize the latch circuit to a through state in response to the reset instructions supplied to the second external terminals.

18. The semiconductor device according to claim 12, further comprising:

a memory controller coupled to the first and second interface circuits by an internal bus; and

a non-volatile memory coupled to the memory controller.

19. The semiconductor device according to claim 18, further comprising a microcomputer coupled to third external terminals.

20. The semiconductor device according to claim 19,

wherein the first external terminal is defined as a clock terminal,

wherein the second external terminals are defined as a data terminal and a command terminal when used in the interface operation of the first interface circuit, and defined as a non-inverted data terminal and an inverted data terminal when used in the interface operation of the second interface circuit, and

wherein the third external terminals are defined as a reset terminal, a clock terminal, and an input/output terminal.

21. A semiconductor device comprising:

a first interface circuit for interfacing signals using a pair of second external terminals, upon receiving a clock input from a first external terminal;

a second interface circuit for interfacing differential signals using the second external terminals, without receiving a clock input from the outside;

a first high-resistance DC circuit for initializing the second external terminals to a first level in response to the start of power supply;

a selection control circuit for enabling, after start of power supply, an interface operation of the first interface circuit by a first instruction signal upon detection of a plurality of edge changes in the clock input from the first external terminal in order to initialize the first interface circuit, while enabling the interface operation of the second interface circuit by a second instruction signal upon detection of a second level supplied to the second external terminals that were initialized to the first level; and

a second high-resistance DC circuit for changing one of the second external terminals to the first level in response to the detection of the second level by the selection control circuit, so that the coupling of the second interface circuit can be recognized from the outside of the second external terminal.

22. The semiconductor device according to claim 21,

wherein the first interface circuit determines that the instruction state by the first instruction signal is a defined state at a predetermined timing after the start of power supply, and outputs a first mask signal for fixing the state of the second instruction signal to a disable instruction state, and

wherein the second interface circuit determines that the instruction state by the second instruction signal is a defined state at a predetermined timing after the start of power supply, and outputs a second mask signal for fixing the state of the first instruction signal to a disable instruction state.

23. The semiconductor device according to claim 22,

wherein, when the interface operation of the first interface circuit is enabled, the first interface circuit releases the disable instruction state to the second instruction signal in response to reset instructions supplied to the second external terminals, and

wherein, when the interface operation of the second interface circuit is enabled, the second interface circuit releases the disable instruction state to the first instruction signal in response to reset instructions supplied to the second external terminals.

24. The semiconductor device according to claim 22, further comprising:

a first latch circuit for latching the detection result obtained by a plurality times of detection; and

a second latch circuit for latching the detection result obtained by detecting the second level,

wherein the first and second latch circuits perform latch operation due to the disable instruction state to the second instruction signal by the first mask signal, or due to the disable instruction state to the first instruction signal by the second mask signal.

25. The semiconductor device according to claim 24,

wherein, when the interface operation of the first interface circuit is enabled, the first interface circuit initializes the first and second latch circuits to a through state in response to the reset instructions supplied to the second external terminals, and

wherein, when the interface operation of the second interface circuit is enabled, the second interface circuit initializes the first and second latch circuits to a through state in response to the reset instructions supplied to the second external terminals.

26. The semiconductor device according to claim 21, further comprising:

a memory controller coupled to the first and second interface circuits by an internal bus; and

a non-volatile memory coupled to the memory controller.

27. The semiconductor device according to claim 26, further comprising a microcomputer coupled to third external terminals.

28. The semiconductor device according to claim 27,

wherein the first external terminal is defined as a clock terminal,

wherein the second external terminals are defined as a data terminal and a command terminal when used in the interface operation of the first interface circuit, and defined as a non-inverted data terminal and an inverted data terminal when used in the interface operation of the second interface circuit, and

wherein the third external terminals are defined as a reset terminal, a clock terminal, and an input/output terminal.