IC CARD
First Claim
1. A semiconductor device comprising:
- a first interface circuit for interfacing signals using second external terminals, upon receiving a clock input from a first external terminal;
a second interface circuit for interfacing differential signals using the second external terminals, without receiving a clock input from the outside; and
a selection control circuit for detecting an input of a plurality of first clocks from the first external signal at the start of power supply, and outputting an activation signal of a first instruction signal to enable the interface operation of the first interface circuit.
3 Assignments
0 Petitions
Accused Products
Abstract
Disclosed is a semiconductor device including built-in interface circuits whose operations are selected in response to initialization operation from a host apparatus coupled thereto. In the semiconductor device, a first synchronous interface circuit and a second asynchronous interface circuit using differential signals, share the external terminals of the differential signals (the external differential signal terminals). For example, the semiconductor device adopts an MMC interface circuit as the first interface circuit and a USB interface circuit as the second interface circuit, while keeping the IC card interface function. The semiconductor device selects operations of the adopted interface circuits exclusively. One selection method is to enable an interface operation of the first interface circuit, upon detection of a plurality of edge changes in a clock input from an external clock terminal, which is for initializing the first interface circuit when power supply to the semiconductor device is started.
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Citations
32 Claims
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1. A semiconductor device comprising:
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a first interface circuit for interfacing signals using second external terminals, upon receiving a clock input from a first external terminal; a second interface circuit for interfacing differential signals using the second external terminals, without receiving a clock input from the outside; and a selection control circuit for detecting an input of a plurality of first clocks from the first external signal at the start of power supply, and outputting an activation signal of a first instruction signal to enable the interface operation of the first interface circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 29, 30, 31, 32)
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12. A semiconductor device comprising:
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a first interface circuit for interfacing signals using a pair of second external terminals, upon receiving a clock input from a first external terminal; a second interface circuit for interfacing differential signals using the second external terminals, without receiving a clock input from the outside; a first high-resistance DC circuit for initializing the second external terminals to a first level in response to the start of power supply; a selection control circuit for enabling an interface operation of the second interface circuit by a first instruction signal, upon detection of a second level supplied to the initialized second external terminals; and a second high-resistance DC circuit for changing the one of the second external terminals to a first level in response to the detection of the second level by the selection control circuit, so that the coupling of the second interface circuit can be recognized from the outside of the second external terminal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A semiconductor device comprising:
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a first interface circuit for interfacing signals using a pair of second external terminals, upon receiving a clock input from a first external terminal; a second interface circuit for interfacing differential signals using the second external terminals, without receiving a clock input from the outside; a first high-resistance DC circuit for initializing the second external terminals to a first level in response to the start of power supply; a selection control circuit for enabling, after start of power supply, an interface operation of the first interface circuit by a first instruction signal upon detection of a plurality of edge changes in the clock input from the first external terminal in order to initialize the first interface circuit, while enabling the interface operation of the second interface circuit by a second instruction signal upon detection of a second level supplied to the second external terminals that were initialized to the first level; and a second high-resistance DC circuit for changing one of the second external terminals to the first level in response to the detection of the second level by the selection control circuit, so that the coupling of the second interface circuit can be recognized from the outside of the second external terminal. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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Specification