STRESS LAYER STRUCTURE

• US 20080246061A1
• Filed: 04/03/2007
• Published: 10/09/2008
• Est. Priority Date: 04/03/2007
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liu, Chih-Chien, Yang, Chin-Sheng
• Application Number:
  US11/695,761
• Publication Number:
  US 20080246061A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each of the stress patterns is disposed on the substrate of each of the active regions, respectively. The partition line exposes a portion of the substrate and divides the two adjacent stress patterns. The dummy stress pattern is disposed on the substrate in the partition line.

Claims

1. A stress layer structure disposed on a substrate comprising a device region and a non-device region, the device region comprising a plurality of active regions and a non-active region, the stress layer structure comprising:

a plurality of stress patterns disposed on the substrate of each of the active regions, respectively;

at least a partition line exposing a portion of the substrate and dividing the two adjacent stress patterns; and

at least a dummy stress pattern disposed on the substrate in said partition line.

2. The stress layer structure of claim 1, wherein the material of the stress patterns comprises silicon nitride.

3. The stress layer structure of claim 1, wherein the material of said dummy stress pattern comprises silicon nitride.

4. The stress layer structure of claim 1, wherein said dummy stress pattern is further disposed on the substrate of the non-device region.

5. The stress layer structure of claim 1, wherein the substrate of the non-device region comprises a polysilicon conductive line, and said dummy stress pattern is further disposed on the polysilicon conductive line.

6. The stress layer structure of claim 1, wherein the substrate of the non-device region comprises the polysilicon conductive line, and said dummy stress pattern is further disposed on a part of the polysilicon conductive line.

7. The stress layer structure of claim 1, wherein each of the active regions comprises a MOS transistor region and a non-MOS transistor region, and the stress layer structure further comprises a dummy opening disposed in each of the stress patterns of the non-MOS transistor region.

8. The stress layer structure of claim 1, wherein the area of said dummy stress pattern occupies 1%˜

99% of the total area of the substrate.

9. A stress layer structure disposed on a substrate comprising a device region and a non-device region, the device region comprising an active region and a non-active region, the active region comprising a MOS transistor region and a non-MOS transistor region, the stress layer structure comprising:

a plurality of stress layers disposed on the substrate of the device region and of the non-device region, respectively; and

a plurality of dummy openings disposed in the stress layers outside the MOS transistor region.

10. The stress layer structure of claim 9, wherein the material of the stress layers comprises silicon nitride.

11. The stress layer structure of claim 9, wherein each of the dummy openings is further disposed in the non-MOS transistor region.

12. The stress layer structure of claim 9, wherein each of the dummy openings is further disposed at the corner of each of the stress layers.

13. The stress layer structure of claim 9, wherein the substrate of the non-device region comprises a polysilicon conductive line, and each of the dummy openings is further disposed on the polysilicon conductive line.

14. The stress layer structure of claim 9, wherein the substrate of the non-device region comprises the polysilicon conductive line, and each of the dummy openings is further disposed on a part of the polysilicon conductive line.

15. The stress layer structure of claim 9, wherein the total area of the dummy openings occupies 1%˜

99% of the total area of the substrate.

16. A stress layer structure disposed on a substrate comprising a device region and a non-device region, the device region comprising a plurality of active regions and a non-active region, the active regions comprising an N-type active region and a P-type active region, the stress layer structure comprising:

a plurality of stress patterns, comprising;

at least a tensile stress pattern disposed on the substrate of the N-type active region; and

at least a compressive stress pattern disposed on the substrate of the P-type active region;

at least a partition line dividing the two adjacent stress patterns; and

a plurality of dummy stress patterns, comprising;

at least a dummy tensile stress pattern disposed on the substrate in said partition line; and

at least a dummy compressive stress pattern disposed on the substrate in said partition line.

17. The stress layer structure of claim 16, wherein the material of the stress patterns comprises silicon nitride.

18. The stress layer structure of claim 16, wherein the material of the dummy stress patterns comprises silicon nitride.

19. The stress layer structure of claim 16, wherein each of the dummy stress patterns is further disposed on the substrate of the non-device region.

20. The stress layer structure of claim 16, wherein the substrate of the non-device region comprises a polysilicon conductive line, and each of the dummy stress patterns is further disposed on the polysilicon conductive line.

21. The stress layer structure of claim 16, wherein the substrate of the non-device region comprises the polysilicon conductive line, and each of the dummy stress patterns is further disposed on a part of the polysilicon conductive line.

22. The stress layer structure of claim 16, wherein each of the active regions comprises a MOS transistor region and a non-MOS transistor region, and the stress layer structure further comprises a dummy opening disposed in each of the stress patterns of the non-MOS transistor region.

23. The stress layer structure of claim 16, wherein the area of the dummy stress patterns occupies 1%˜

99% of the total area of the substrate.