Dram device and method of manufacturing the same

• US 20080246067A1
• Filed: 05/01/2008
• Published: 10/09/2008
• Est. Priority Date: 03/05/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoon, Hong-Sik, Yeo, In-Seok, Huo, Zong-Liang, Baik, Seung-Jae, Kim, Shi-Eun
• Granted Patent: US 7,795,659 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

Claims

1. A dynamic random access memory (DRAM) structure comprising:

a multiple tunnel junction (MTJ) structure including conductive patterns and nonconductive patterns alternately stacked on each other, the nonconductive patterns having a band gap larger than a band gap of the conductive patterns;

a first insulation layer arranged on a sidewall of the MTJ structure;

a gate electrode arranged on the gate insulation layer;

a word line electrically connected with the MTJ structure;

a bit line electrically connected with one of a top surface and a bottom surface of the MTJ structure; and

a capacitor electrically connected with one of a top surface and a bottom surface of the MTJ structure that is not connected with the bit line.

2. The DRAM structure of claim 1, wherein the gate electrode and the word line are integrally formed.

3. The DRAM structure of claim 1, wherein a storage electrode of the capacitor is integrally formed with one of the top surface and the bottom surface of the MTJ structure.

4. The DRAM structure of claim 1, wherein

the capacitor is formed on a substrate;

the MTJ structure contacts the capacitor;

the bit line is formed on the MTJ structure in a first direction;

the first insulation layer is formed on a top surface of the capacitor, on a sidewall of the MTJ structure and on a top surface of the bit line; and

the word line is formed integrally with the gate electrode on the first insulation layer in a second direction perpendicular to the first direction, the word line facing the sidewall of the MTJ structure.

5. The DRAM structure of claim 4, wherein the capacitor includes:

a plate electrode formed on the substrate into a column shape vertically extending from a surface of the substrate, so that a space is formed between adjacent column-shaped plate electrodes;

a capacitor dielectric layer formed on a sidewall of the plate electrode and the surface of the substrate in the space; and

a storage electrode formed on the capacitor dielectric layer in the space, the storage electrode including a conductive material.

6. The DRAM structure of claim 5, wherein the storage electrode includes polysilicon doped with impurities.

7. The DRAM structure of claim 5, wherein a top surface of the plate electrode is substantially coplanar with a top surface of the storage electrode.

8. The DRAM structure of claim 5, further comprising:

a second insulation layer formed on a top surface of the plate electrode, the top surface of the plate electrode is lower than a top surface of the storage electrode, the second insulation layer reducing a parasitic capacitance.

9. The DRAM structure of claim 4, further comprising a boundary conductive layer between the substrate and the capacitor.

10. The DRAM structure of claim 4, further comprising a device isolation pattern formed between adjacent capacitors in a second direction perpendicular to the first direction.

11. The DRAM structure of claim 4, wherein the MTJ structure includes n conductive patterns and (n−

1) nonconductive patterns that are sequentially interposed between adjacent conductive patterns, a first and an n^th conductive pattern including polysilicon doped with first polarity type impurities, and residual conductive patterns except the first and the n^th conductive patterns including polysilicon doped with second polarity type impurities that are different from the first polarity type impurities, and n is an integer less than 4.

12. The DRAM structure of claim 11, wherein the first conductive pattern is integrally formed together with a storage electrode of the capacitor.

13. The DRAM structure of claim 4, wherein the nonconductive patterns includes at least one of silicon nitride, silicon oxide, metal oxide and combinations thereof.

14. The DRAM structure of claim 4, further comprising:

a hard mask pattern formed on the bit line.

15. A dynamic random access memory (DRAM) device comprising:

a first DRAM structure according to claim 4, wherein a first conductive layer is interposed between the capacitor of the first DRAM structure and the substrate;

a first insulation interlayer formed on the first DRAM structure with a thickness sufficient to cover the DRAM structure;

a second conductive layer formed on the first insulation interlayer; and

a second DRAM structure according to claim 4 formed on the second conductive layer.

27. A method of manufacturing a dynamic random access memory (DRAM) device, comprising:

forming a first DRAM structure according to claim 4 with a first conductive layer interposed between the first DRAM structure and the substrate;

forming a first insulation interlayer on the first DRAM structure with a thickness sufficient to cover the first insulation interlayer;

forming a second conductive layer on the first insulation interlayer; and

forming a second DRAM structure according to claim 4 on the second conductive layer.

16-26. -26. (canceled)