Self-Aligned Trench MOSFET and Method of Manufacture

• US 20080246081A1
• Filed: 01/17/2008
• Published: 10/09/2008
• Est. Priority Date: 04/03/2007
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Chen, Kuo-In, Li, Jian, Terril, Kyle
• Granted Patent: US 9,947,770 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

Claims

1. A trench metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a drain region;

a body region disposed above the drain region;

a gate region disposed within the body region;

a gate insulator region disposed about a periphery of the gate region;

a field insulator region disposed above the gate region;

a plurality of source regions disposed along the surface of the body region proximate a periphery of the gate insulator region;

a plurality of source/body contact spacers disposed in recessed mesas above the plurality of source regions and between the gate insulator region, wherein the recessed mesas are formed by a first silicon etch self-aligned to the field insulator region;

a plurality of source/body contact plugs disposed through the source/body contact spacers and the plurality of source regions between the gate insulator region; and

a plurality of source/body contact implants disposed in the body region proximate the source/body contacts, wherein the source/body contacts implants are formed by an implant self-aligned to the plurality of source body contact spacers.

2. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1, wherein the gate region is formed as a plurality of substantially parallel elongated structures.

3. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1, wherein:

a first portion of the gate region is formed as a first plurality of substantially parallel elongated structures; and

a second portion of the gate region is formed as a second plurality of substantially parallel elongated structures that are substantially perpendicular to the first plurality of substantially parallel elongated structures.

4. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1, wherein;

the drain region comprises an n-doped semiconductor;

the body region comprises a p-doped semiconductor;

the gate insulator region comprises an oxide;

the plurality of source regions comprise a heavily n-doped semiconductor; and

the gate region comprises a heavily n-doped semiconductor.

5. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 4, wherein the drain region comprises:

a first portion comprises a heavily n-doped semiconductor; and

a second portion comprises a lightly n-doped semiconductor disposed between the body region and the first portion.

6. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 1, wherein;

the drain region comprises an p-doped semiconductor;

the body region comprises a n-doped semiconductor;

the gate insulator region comprises an oxide;

the plurality of source regions comprise a heavily p-doped semiconductor; and

the gate region comprises a heavily p-doped semiconductor.

7. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 6, wherein the drain region comprises:

a first portion comprises a heavily p-doped semiconductor; and

a second portion comprises a lightly p-doped semiconductor disposed between the body region and the first portion.

8. A trench metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

a drain region;

a plurality of gate regions disposed above the drain region;

a plurality of gate insulator regions, wherein each of the plurality of gate insulator regions are disposed about a periphery of a respective one of the plurality of gate regions;

a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions;

a plurality of body regions disposed in the recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region;

a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions

a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas;

a source/body contact disposed above the source/body contact spacers; and

a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

9. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 8, wherein the gate region is formed as a plurality of substantially parallel elongated structures.

10. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 8, wherein:

a first portion of the gate region is formed as a first plurality of substantially parallel elongated structures; and

a second portion of the gate region is formed as a second plurality of substantially parallel elongated structures that are substantially perpendicular to the first plurality of substantially parallel elongated structures.

11. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 8, wherein;

the drain region comprises an n-doped semiconductor;

the gate region comprises a n-doped semiconductor;

the gate insulator region comprises an oxide;

the plurality of source regions comprise a heavily n-doped semiconductor;

the body region comprises a p-doped semiconductor;

the plurality of body contact regions comprise a heavily p-doped semiconductor;

the plurality of source/body contact spacers comprise an oxide;

the source/body contact comprise a first metal; and

the plurality of source/body contact plugs comprise a second metal.

12. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 8, wherein;

the first metal comprises aluminum; and

the second metal comprises tungsten.

13. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 8, further comprising a drift region disposed between the drain region and the body region.

14. The trench metal-oxide-semiconductor field effect transistor (MOSFET) of claim 13, wherein:

the drain region comprises a heavily n-doped semiconductor; and

the drift region comprises a lightly n-doped semiconductor.

15. A method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) comprising:

depositing a first semiconductor layer upon a semiconductor substrate, wherein the first semiconductor layer and the semiconductor substrate are doped with a first type of impurity;

doping a first portion of the first semiconductor layer with a second type of impurity;

etching a plurality of trenches in the first semiconductor layer;

forming a first dielectric layer on the wall of the plurality of trenches;

depositing a second semiconductor layer in the plurality of trenches;

forming a second dielectric layer over the second semiconductor layer in the plurality of trenches;

etching recessed mesas in the first semiconductor layer self-aligned by the first and second dielectric layers;

doping a second portion of the first semiconductor layer proximate the recessed mesas with a second type of impurity;

forming a plurality of source/body contact spacers in the recessed mesas self-aligned by the second dielectric layer in the trenches;

etching a plurality of source/body contact trenches between the source/body contact spacers, wherein the source body contact trenches extend through the second portion of the first semiconductor layer;

doping a third portion of the first semiconductor layer proximate the source/body contact trenches with the first type of impurity self-aligned by the source/body contact spacers; and

deposit a first metal layer in the source/body contact trenches.

16. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to claim 15, wherein a first set of the plurality of trenches are substantially parallel with respect to each other and a second set of the plurality of trenches are normal-to-parallel with respect to the first set of the plurality of trenches

17. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to claim 15, wherein the plurality of trenches are substantially parallel with respect to each other.

18. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 15, further comprising forming a silicide on the second semiconductor layer in the plurality of trenches.

19. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 15, wherein forming the second dielectric over the second semiconductor in the plurality of trenches comprises:

depositing the dielectric layer; and

removing excess dielectric until the first semiconductor layer is exposed and the second dielectric covers the first semiconductor layer in the plurality of trenches.

20. The method of fabrication a trench metal-oxide-semiconductor field effect transistor (MOSFET) according to 15, wherein forming the plurality of source/body contact spacers comprises:

conformally depositing a third dielectric layer after doping the second portion of the first semiconductor layer; and

etching the third dielectric layer whereby the portions of the third dielectric layer substantially remain along vertical sides the second dielectric layer proximate the recessed mesas.