INTEGRATED PASSIVE DEVICE WITH A HIGH RESISTIVITY SUBSTRATE AND METHOD FOR FORMING THE SAME

• US 20080246114A1
• Filed: 04/09/2007
• Published: 10/09/2008
• Est. Priority Date: 04/09/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Cotronakis, James G., Daly, Terry K., Fender, Jason R., Abrokwah, Jonathan K., Costello, Keri L., Reyes, Adolfo C.
• Granted Patent: US 7,935,607 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 27/016 Thin-film circuits

Abstract

According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the insulating dielectric layer (32).

Claims

1. A method of forming an integrated passive device (IPD) comprising:

forming an oxide layer having a thickness of at least 4 microns over a silicon substrate, the oxide layer comprising tetraethyl orthosilicate (TEOS) oxide; and

forming at least one passive electronic component over the insulating dielectric oxide layer.

2. The method of claim 1, wherein the insulating dielectric layer is an the at least one passive electronic component comprises at least one of a capacitor, a resistor, and an inductor.

4. The method of claim 2, wherein the at least one passive electronic component comprises a plurality of passive electronic components.

5. The method of claim 4, wherein said formation of the oxide layer occurs at a temperature that is less than approximately 550°

C.

6. The method of claim 5, wherein said formation of the oxide layer occurs at a temperature that is between approximately 150°

C. and 550°

C.

8. The method of claim 6, wherein the thickness of the oxide layer is between approximately 4 and 20 microns.

9. The method of claim 8, wherein the thickness of the oxide layer is between approximately 4 and 6 microns.

10. The method of claim 9, wherein the silicon substrate has a thickness of between approximately 25 and 800 microns and a resistivity of greater than 1000 ohm-cm.

3. (canceled)

7. (canceled)

11. A method for forming an integrated passive device (IPD) comprising:

providing a silicon substrate with a resistivity greater than 1000 ohm-cm;

forming a tetraethyl orthosilicate (TEOS) oxide layer having a thickness of at least 4 microns over the silicon substrate, said formation of the TEOS oxide layer occurring at a temperature that is less than 550°

C.; and

forming a plurality of passive electronic components over the TEOS oxide layer.

12. The method of claim 11, wherein the TEOS oxide layer is formed using chemical vapor deposition.

13. The method of claim 12, wherein the plurality of passive electronic components comprises at least one of a capacitor, a resistor, and an inductor and said formation of the plurality of passive electronic components comprises:

forming a first conductive layer over the TEOS oxide layer; and

forming a second conductive layer over the first conductive layer.

14. The method of claim 13, wherein said formation of the TEOS oxide layer occurs at a temperature that is between approximately 150°

C. and 450°

C.

15. The method of claim 14, wherein the silicon substrate has a thickness of between approximately 25 and 625 microns and the thickness of the TEOS oxide layer is between approximately 4 and 6 microns.

16. A microelectronic assembly comprising:

a silicon substrate with a resistivity of at least 1000 ohm-cm;

a tetraethyl orthosilicate (TEOS) oxide layer having a thickness of at least 4 microns formed over the silicon substrate; and

a plurality of passive electronic components formed over the TEOS oxide layer.

17. The microelectronic assembly of claim 16, wherein the thickness of the TEOS oxide layer is between 4 and 6 microns.

18. The microelectronic assembly of claim 17, wherein the plurality of passive electronic components comprises at least one of a capacitor, a resistor, and an inductor.

19. The microelectronic assembly of claim 18, wherein the plurality of passive electronic components jointly form a harmonic filter.

20. The microelectronic assembly of claim 19, further comprising an integrated circuit coupled to the plurality of passive electronic components.