Sleep mode control circuit and method for a DC/DC switching power supply system

• US 20080246448A1
• Filed: 04/01/2008
• Published: 10/09/2008
• Est. Priority Date: 04/04/2007
• Status: Active Grant

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: Chiu, Wei-Che
• Granted Patent: US 7,576,601 B2
• Time in Patent Office: Days
• US Class Current: 323/234
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A sleep mode control circuit and method are provided to pull high the error signal of a DC/DC switching power supply system to a target level when the switching power supply system is in a sleep mode, such that the switching power supply system can be more rapidly waked up from the sleep mode to its normal mode once the loading of the switching power supply system increases. A threshold is given for the output signal of the comparator that is used to determine the duty for the switching power supply system, and the error signal in the sleep mode is thus maintained slightly lower than the minimum voltage for the error signal in the normal mode.

Claims

1. A sleep mode control circuit for a DC/DC switching power supply system including an error amplifier to provide an error signal on its output node, and a comparator to compare the error signal with an oscillating signal to produce an output signal on its output node, the sleep mode control circuit comprising:

a level setting circuit connected between the output node of the comparator and the output node of the error amplifier, for pulling high the error signal to a target level when the output signal in a sleep mode is lower than a threshold; and

a sleep mode indicator for enabling the level setting circuit when the switching power supply system enters the sleep mode.

2. The sleep mode control circuit of claim 1, wherein the level setting circuit comprises:

a transistor connected between a power source and the output node of the error amplifier; and

a second comparator for turning on the transistor when the output signal in the sleep mode is lower than the threshold, so as to inject a current to the output node of the error amplifier.

3. The sleep mode control circuit of claim 1, wherein the threshold is lower than a level that the output signal will be such that the switching power supply system enters the sleep mode.

6. The sleep mode control circuit of claim 1, wherein the threshold is lower than a level that the output signal will be such that the switching power supply system enters the sleep mode.

4. A sleep mode control circuit for a DC/DC switching power supply system including an error amplifier to provide an error signal on its output node, a compensation circuit connected to the output node of the error amplifier to compensate the error signal, and a comparator to compare the compensated error signal with an oscillating signal to produce an output signal on its output node, the sleep mode control circuit comprising:

a level setting circuit connected between the output node of the comparator and the compensation circuit, for injecting a circuit into the compensation circuit to pull high the error signal to a target level when the output signal in a sleep mode is lower than a threshold; and

a sleep mode indicator for enabling the level setting circuit when the switching power supply system enters the sleep mode.

5. The sleep mode control circuit of claim 4, wherein the level setting circuit comprises:

a transistor connected between a power source and the output node of the error amplifier; and

a second comparator for turning on the transistor when the output signal in the sleep mode is lower than the threshold so as to inject the current to the compensation circuit.

7. A sleep mode control method for a DC/DC switching power supply system including an error amplifier to provide an error signal on its output node, and a comparator to compare the error signal with an oscillating signal to produce an output signal on its output node, the sleep mode control method comprising the steps of:

A. monitoring the output signal when the switching power supply is in a sleep mode; and

B. pulling high the error signal to a target level when the output signal in the sleep mode is lower than a threshold.

8. The sleep mode control method of claim 7, wherein the step B comprises the step of injecting a current to the output node of the error amplifier.