Phase Change Memory Bridge Cell with Diode Isolation Device

• US 20080247224A1
• Filed: 04/06/2007
• Published: 10/09/2008
• Est. Priority Date: 04/06/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang Lan
• Granted Patent: US 8,610,098 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/5664 using organic memory material storage elements
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/041 Modification of the switching material, e.g. post-treatment, doping
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

Memory cells are described along with arrays and methods for manufacturing. An embodiment of a memory cell as described herein includes a second doped semiconductor region on a first doped semiconductor region and defining a pn junction therebetween. A first electrode on the second doped semiconductor region. An insulating member between the first electrode and a second electrode, the insulating member having a thickness between the first and second electrodes. A bridge of memory material across the insulating member, the bridge having a bottom surface and contacting the first and second electrodes on the bottom surface, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.

Claims

1. A memory device, comprising:

a first doped semiconductor region having a first conductivity type;

a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the second doped semiconductor region on the first doped semiconductor region and defining a pn junction therebetween;

a first electrode on the second doped semiconductor region;

a second electrode;

an insulating member between the first electrode and the second electrode, the insulating member having a thickness between the first and second electrodes; and

a bridge of memory material across the insulating member, the bridge having a bottom surface and contacting the first and second electrodes on the bottom surface, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.

2. The device of claim 1, wherein the at least two solid phases are reversibly inducible by a current.

3. The device of claim 2, wherein the at least two solid phases include a generally amorphous phase and a generally crystalline phase.

4. The device of claim 1, wherein the thickness of the insulating member is less than a minimum lithographic feature size for a lithographic process used to form the device.

5. The device of claim 1, wherein the memory material comprises an alloy including a combination of Ge, Sb, and Te.

6. The device of claim 1, wherein the memory material comprises an alloy including a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.

7. The device of claim 1, wherein the first conductivity type comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

8. The device of claim 1, wherein the first and second electrodes comprise an element selected from a group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof.

9. The device of claim 1, wherein the first and second electrodes comprise Ti and N.

10. The device of claim 1, wherein the first and second electrodes comprise Ta and N.

11. An array of memory cells, the array comprising:

a plurality of word lines comprising doped semiconductor material having a first conductivity type, the word lines having word line widths and extending in parallel in a first direction;

a plurality of second doped semiconductor regions having a second conductivity type opposite the first conductivity type, second doped semiconductor regions in the plurality of second doped semiconductor regions on corresponding word lines and defining respective pn junctions therebetween;

a plurality of electrode pairs, wherein pairs include respective first and second electrodes and an insulating member between the first and second electrodes, the insulating member having a thickness between the first and second electrodes, the first electrodes on corresponding second doped semiconductor regions; and

an array of bridges of memory material across the insulating members of respective electrode pairs, the bridges having respective bottom surfaces and contacting the first and second electrodes in the respective electrode pairs on the bottom surface, and defining an inter-electrode path between the corresponding first and second electrodes defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.

12. The array of memory cells of claim 11, wherein the memory cells in the array of memory cells include (a) a pn junction, (b) an electrode pair, and (c) a bridge of memory material, such that the memory cells are arranged in a cross point array.

13. The array of memory cells of claim 12, further comprising a plurality of conductive bit lines including second electrodes in the plurality of electrode pairs, the bit lines having bit line widths and extending in parallel in a second direction perpendicular to the first direction.

14. The array of memory cells of claim 13, further comprising:

adjacent bit lines in the plurality of bit lines being separated by a first separation distance;

adjacent word lines in the plurality of word lines being separated by a second separation distance; and

memory cells in the array of memory cells having a memory cell area, the memory cell area having a first side along the first direction and a second side along the second direction, the first side having a length equal to the word line width and the second separation distance, and the second side having a length equal to the bit line width and the first separation distance.

15. The array of memory cells of claim 14, wherein the first side length is equal to twice a feature size F, and the second side is equal to twice a feature size F, such that the memory cell area is equal to about 4F².

16. The array of memory cells of claim 11, wherein the at least two solid phases are reversibly inducible by a current.

17. The array of memory cells of claim 11, wherein the at least two solid phases include a generally amorphous phase and a generally crystalline phase.

18. The array of memory cells of claim 11, wherein the thickness of the insulating member is less than a minimum lithographic feature size for a lithographic process used to form the array.

19. The array of memory cells of claim 11, wherein the memory material comprises an alloy including a combination of Ge, Sb, and Te.

20. The array of memory cells of claim 11, wherein the memory material comprises an alloy including a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.

21. The array of memory cells of claim 11, wherein the first conductivity type comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

22. The array of memory cells of claim 11, wherein the first and second electrodes comprise an element chosen from a group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof.

23. The array of memory cells of claim 11, wherein the first and second electrodes comprise Ti and N.

24. The array of memory cells of claim 11, wherein the first and second electrodes comprise Ta and N.

25. A method for manufacturing an array of memory cells, the method comprising:

forming a plurality of word lines comprising doped semiconductor material having a first conductivity type, the word lines having word line widths and extending in parallel in a first direction;

forming a plurality of second doped semiconductor regions, having a second conductivity type opposite the first conductivity type, on corresponding word lines and defining respective pn junctions therebetween;

forming a plurality of electrode pairs, wherein pairs include respective first and second electrodes and an insulating member between the first and second electrodes, the insulating member having a thickness between the first and second electrodes, the first electrodes on corresponding second doped semiconductor regions; and

forming an array of bridges of memory material across the insulating members of respective electrode pairs, the bridges having respective bottom surfaces and contacting the first and second electrodes in the respective electrode pairs on the bottom surface, and defining an inter-electrode path between the corresponding first and second electrodes defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.

26. The method of claim 25, wherein the memory cells in the array of memory cells include (a) a pn junction, (b) an electrode pair, and (c) a bridge of memory material, such that the memory cells are arranged in a cross point array.

27. The method of claim 26, further comprising forming a plurality of conductive bit lines including second electrodes in the plurality of electrode pairs, the bit lines having bit line widths and extending in parallel in a second direction perpendicular to the first direction.

28. The method of claim 27, further comprising:

adjacent bit lines in the plurality of bit lines being separated by a first separation distance;

adjacent word lines in the plurality of word lines being separated by a second separation distance; and

memory cells in the array of memory cells having a memory cell area, the memory cell area having a first side along the first direction and a second side along the second direction, the first side having a length equal to the word line width and the second separation distance, and the second side having a length equal to the bit line width and the first separation distance.

29. The method of claim 28, wherein the first side length is equal to twice a feature size F, and the second side length is equal to twice the feature size F, such that the memory cell area is equal to about 4F².

30. The method of claim 25, wherein the at least two solid phases are reversibly inducible by a current.

31. The method of claim 25, wherein the at least two solid phases include a generally amorphous phase and a generally crystalline phase.

32. The method of claim 25, wherein the thickness of the insulating member is less than a minimum lithographic feature size for a lithographic process used to form the array.

33. The method of claim 25, wherein the memory material comprises an alloy including a combination of Ge, Sb, and Te.

34. The method of claim 25, wherein the memory material comprises an alloy including a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.

35. The method of claim 25, wherein the first conductivity comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

36. The method of claim 25, wherein the first and second electrodes comprise an element chosen from a group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof.

37. The method of claim 25, wherein the first and second electrodes comprise Ti and N.

38. The method of claim 25, wherein the first and second electrodes comprise Ta and N.

39. A method for manufacturing an array of memory cells, the method comprising:

patterning a multi-layer structure to form a plurality of strips from the multi-layer structure, the strips extending in parallel in a first direction and defining a plurality of first trenches therebetween, wherein the strips in the plurality of strips include (a) a wordline comprising a first doped semiconductor layer having a first conductivity type, (b) a second doped semiconductor layer on the wordline, the second doped semiconductor layer having a second conductivity type, and (c) a conductive bottom electrode layer comprising bottom electrode material on the second doped semiconductor layer;

forming a first dielectric material in the plurality of first trenches;

forming a plurality of second trenches extending in parallel in a second direction perpendicular to the first direction, thereby exposing portions of the wordlines beneath the second trenches and defining a plurality of multi-layer stacks between the second trenches, the multi-layer stacks having respective top and sidewall surfaces, wherein the multi-layer stacks in the plurality of multi-layer stacks include (a) a second doped region comprising a portion of the second doped semiconductor layer on the corresponding word line and defining a pn junction therebetween, and (b) a first electrode comprising bottom electrode material on the corresponding second doped region;

forming a sidewall dielectric layer over the multi-layer stacks and planarizing to expose the top surfaces of the multi-layer stacks, thereby forming a plurality of insulating members on the sidewall surfaces of the multi-layer stacks such that pairs of insulating members are between adjacent first electrodes;

forming a plurality of bit lines extending in parallel in the second direction, bit lines in the plurality of bit lines between pairs of insulating members;

patterning a layer of memory material to form a plurality of bridges, thereby forming an array of memory cells, the bridges extending across one of the insulating members in the pair of insulating members between adjacent first electrodes, the bridges having respective bottom surfaces and contacting the corresponding first electrodes and bit lines, and defining an inter-electrode path between the corresponding first electrodes and bit lines defined by the thickness of the corresponding insulating member, wherein the memory material has at least two solid phases.