Gated semiconductor device and method of fabricating same

• US 20080248620A1
• Filed: 04/09/2007
• Published: 10/09/2008
• Est. Priority Date: 04/09/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Shih-Chang, Tsai, Chia-Shiung, Shen, Ming-Hui, Lo, Chi-Hsin, Chu, Yi-Shin
• Granted Patent: US 7,700,473 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: Y10S 438/945 Special, e.g. metal

Abstract

A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Claims

1. A method for fabricating a semiconductor device, comprising:

forming at least one hard mask, each hard mask comprising an oxide layer disposed between an upper nitride layer and a lower nitride layer;

reducing a lateral dimension of the hard mask oxide layer to less than the corresponding lateral dimension of the hard mask upper nitride layer;

forming a gate structure on a substrate using each hard mask, each gate structure comprising a first spacer layer, the first spacer layer conforming to the dimensions of the hard mask oxide layer.

2. The method of claim 1, wherein the at least one hard mask comprises a plurality of hard masks.

3. The method of claim 1, wherein the first spacer layer comprises a nitride layer disposed between an inner oxide layer and an outer oxide layer.

4. The method of claim 1, further comprising:

forming a gate dielectric layer on a substrate; and

forming a first gate layer on the gate dielectric layer prior to forming the at least one hard mask.

5. The method of claim 4, further comprising:

forming an inter-gate dielectric on the first gate layer;

forming a second gate layer on the inter-gate dielectric prior to forming the at least one hard mask.

12. The method of claim 1, wherein the semiconductor device is a flash cell.

6. The method of claim 6, wherein forming the gate structure comprises etching the first gate layer and etching the second gate layer to remove portions thereof that are not protected by the hard mask.

7. The method of claim 6, wherein the etching of the first gate layer and the etching of the second gate layer is done in a single etch step.

8. The method of claim 6, wherein reducing the lateral dimension of the hard mask oxide layer comprises performing a DHF (dilute hydrofluoric acid) dip.

9. The method of claim 8, wherein the DHF dip produces an I-shaped hard mask.

10. The method of claim 6, wherein removing portions of the first gate layer exposes at least one side, and further comprising performing a lateral etch to reduce a lateral dimension thereof.

11. The method of claim 10, further comprising forming an oxide layer on the reduced side of the first gate layer.

13. A method for fabricating a semiconductor device, comprising:

forming at least one gate structure on a substrate, wherein the at least one gate structure comprises a floating gate portion separated from the substrate by a dielectric material and further comprises a control gate separated from the floating gate by an inter-gate dielectric layer, the control gate being bounded by a dielectric spacer that does not bound the floating gate;

etching each floating gate laterally on at least one side to reduce the corresponding lateral dimension; and

forming an oxide layer adjacent the at least one etched side of the floating gate.

14. The method of claim 13, wherein forming the at least one gate structure comprises forming a hard mask and selectively etching the layers of material that have been formed beneath.

15. The method of claim 13, wherein each floating gates comprises poly (polycrystalline silicon).

16. The method of claim 13, wherein the gate structure further comprises a dielectric spacer that does not cover the sides of the floating gates.

17. The method of claim 16, wherein the dielectric spacer comprises a nitride layer disposed between an inner oxide layer and an outer oxide layer.

18. The method of claim 17, wherein the lateral etching reduces at least one side of each floating gate such that the dielectric spacer forms an overhang to be covered by the oxide layer adjacent each floating gate.

19. The method of claim 18, wherein the oxide layer is substantially uniform in thickness where it is adjacent to the floating gate.

20. A semiconductor device, comprising:

a substrate; and

a gate structure, comprising;

a gate electrode;

a lower dielectric layer disposed between the gate electrode and the substrate; and

an upper dielectric layer disposed above the gate electrode, wherein the upper dielectric has an I-shaped profile.

21. The semiconductor device of claim 20, further comprising a second gate structure, the second gate structure disposed on the substrate in a spaced-apart relationship with the gate structure.

22. The semiconductor device of claim 21, wherein the gate structure and the second gate structure are substantially symmetrical about a vertical plane between them.

23. The semiconductor device of claim 21, wherein the semiconductor device is a flash memory cell.

24. The semiconductor device of claim 23, further comprising an erase gate disposed between the gate structure and the second gate structure and separated from each structure by dielectric spacers.

25. The semiconductor device of claim 24, further comprising a wordline structure and a second wordline structure disposed adjacent a side of the gate structure and the second gate structure, respectively, and separated therefrom by a dielectric spacer.

26. The semiconductor device of claim 20, wherein the upper dielectric of comprises an oxide layer disposed between two nitride layers.

27. The semiconductor device of claim 26, wherein the I-shaped profile of the upper dielectric is formed at least in part by a reducing the lateral dimension of the oxide layer after the upper dielectric has been formed.

28. The semiconductor device of claim 20, further comprising a control gate disposed above the gate electrode and separated from it by a layer of dielectric material.

29. The semiconductor device of claim 28, further comprising an oxide layer of substantially uniform thickness adjacent to the at least one side of the gate electrode.