Hybrid power relay using communications link

• US 20080250171A1
• Filed: 04/06/2007
• Published: 10/09/2008
• Est. Priority Date: 04/06/2007
• Status: Active Grant

• Current Assignee: Watlow Electric Manufacturing Company
• Original Assignee: Watlow Electric Manufacturing Company
• Inventors: Lemke, John Frederic, Pfingsten, Thomas Robert, Ness, Keith Douglas, Breitlow, Stanton Hopkins
• Granted Patent: US 7,961,443 B2
• Time in Patent Office: Days
• US Class Current: 710/61
• CPC Class Codes: H01H 2009/545 comprising a parallel semiconductor switch being fired optically, e.g. using a photocoupler,
• CPC Class Codes: H01H 47/007 with galvanic isolation between controlling and controlled circuit, e.g. transformer relay
• CPC Class Codes: H01H 47/32 Energising current supplied by semiconductor device
• CPC Class Codes: H01H 50/021 structurally combining a relay and an electronic component, e.g. varistor, RC circuit auxiliary switch inserting resistor during closure H01H50/543
• CPC Class Codes: H01H 9/542 Contacts shunted by static switch means

Abstract

A control circuit for controlling an arc suppression circuit includes a serial communication link communicating a serial signal therethrough. The control circuit includes a microprocessor having a serial input communicating with the serial communication link. The microprocessor generates a control output signal in response to the serial signal. The control circuit further includes the arc suppression circuit having an electrical contact and operating in response to the control output signal to reduce an arc at the electrical contact.

Claims

1. A control circuit comprising:

a serial communication link communicating a serial signal therethrough;

a microprocessor having a serial input communicating with the serial communication link and generating a control output signal in response to the serial signal; and

an arc suppression circuit having an electrical contact and operating in response to the control output signal to reduce an arc at the electrical contact.

2. A control circuit as recited in claim 1 wherein the serial communication link comprises a two way serial communication link.

3. A control circuit as recited in claim 2 wherein the microprocessor communicates a status signal through the two way serial communication link

4. A control circuit as recited in claim 1 wherein the serial communication link comprises a one way communication link.

5. A control circuit as recited in claim 1 wherein the serial communication link comprises an asynchronous communication link.

6. A control circuit as recited in claim 1 wherein the serial communication link comprises a synchronous communication link.

7. A control circuit as recited in claim 1 wherein the serial communication link is coupled to an interface.

8. A control circuit as recited in claim 7 wherein the interface is disposed within the microprocessor.

9. A control circuit as recited in claim 8 wherein the interface comprises a universal asynchronous receiver transmitter (UART).

10. A control circuit as recited in claim 8 wherein the interface comprises a serial peripheral interface (SPI).

11. A control circuit as recited in claim 8 wherein the interface comprises an inter-integrated circuit (I²C) interface.

12. A control circuit as recited in claim 8 wherein the interface comprises an Ethernet interface.

13. A control circuit as recited in claim 1 wherein the serial signal comprises a serial digital information signal.

14. A control circuit as recited in claim 13 wherein the serial digital information signal comprises a parameter signal.

15. A control circuit as recited in claim 13 wherein the serial digital information signal comprises an algorithm selecting signal.

16. A control circuit as recited in claim 13 wherein the serial digital information signal comprises a state signal corresponding to a desired state of the arc suppression circuit.

17. A control circuit as recited in claim 1 wherein the control output signal comprises a first output signal and a second output signal.

18. A control circuit as recited in claim 17 wherein the arc suppression circuit comprises a mechanical relay portion and a solid state control portion.

19. A control circuit as recited in claim 18 wherein the first output signal controls the mechanical relay control portion and the second output signal controls the solid state control portion

20. A control circuit as recited in claim 18 wherein the first output signal and the second output signal provide coordinated operation of the arc suppression circuit to reduce the arc at the electrical contact.

21. A control circuit as recited in claim 20 wherein the first output signal and the second output signal control a timing of the solid state control portion to be conducting when the electrical contact of the mechanical relay portion is opened or closed.

22. A control circuit as recited in claim 18 wherein the first output signal is electrically isolated from a mechanical relay within the mechanical relay portion.

23. A control circuit as recited in claim 18 wherein the first output signal is electrically isolated from a mechanical relay within the mechanical relay portion with a light emitting diode and a phototransistor.

24. A control circuit as recited in claim 18 wherein the second output signal is electrically isolated from a solid state device within the solid state control portion.

25. A control circuit as recited in claim 18 wherein the second output signal is electrically isolated from a solid state device within the solid state control portion with a photo-triac.

26. A control circuit as recited in claim 1 further comprising a supervisory microprocessor communicating with the microprocessor through the serial communication link.

27. A control circuit as recited in claim 1 further comprising an isolation circuit disposed within the serial communication link.

28. A control circuit as recited in claim 27 wherein the isolation circuit comprises a dual channel digital isolator.

29. A control circuit as recited in claim 1 wherein the microprocessor generates a serial output signal through the serial communication link.

30. A control circuit as recited in claim 29 wherein the serial output signal comprises an error signal.

31. A control circuit as recited in claim 29 wherein the serial output signal comprises a status signal.

32. A control circuit as recited in claim 29 wherein the serial output signal comprises a status signal corresponding to the status of the arc suppression circuit.

33. A method of operating an arc suppression circuit comprising:

receiving a serial signal through a serial communication link;

generating a control output signal in response to the serial signal; and

controlling the arc suppression circuit having an electrical contact with the control output to reduce an arc at the electrical contact.

34. A method as recited in claim 33 wherein the serial communication link comprises a two way serial communication link.

35. A method as recited in claim 34 further comprising communicating a status signal through the two way serial communication link.

36. A method as recited in claim 33 wherein the serial communication link comprises a one way communication link.

37. A method as recited in claim 33 wherein the serial communication link comprises an asynchronous communication link.

38. A method as recited in claim 33 wherein the serial communication link comprises a synchronous communication link.

39. A method as recited in claim 33 further comprising coupling the serial communication link to an interface.

40. A method as recited in claim 39 wherein coupling the serial communication link to an interface comprises coupling the serial communication link to the interface within a microprocessor.

41. A method as recited in claim 39 wherein the interface comprises a universal asynchronous receiver transmitter (UART).

42. A method as recited in claim 39 wherein the interface comprises a serial peripheral interface (SPI).

43. A method as recited in claim 39 wherein the interface comprises an inter-integrated circuit (I²C) interface.

44. A method as recited in claim 39 wherein the interface comprises an Ethernet interface.

45. A method as recited in claim 33 wherein the serial signal comprises a serial digital information signal.

46. A method as recited in claim 45 wherein the serial digital information signal comprises a parameter signal.

47. A method as recited in claim 45 wherein the serial digital information signal comprises an algorithm selecting signal.

48. A method as recited in claim 45 wherein the serial digital information signal comprises a state signal corresponding to a desired state of the arc suppression circuit.

49. A method as recited in claim 33 wherein generating a control output signal comprises generating a first output signal and a second output signal.

50. A method as recited in claim 49 wherein the arc suppression circuit comprises a mechanical relay control portion and a solid state control portion.

51. A method as recited in claim 50 further comprising controlling the mechanical relay control portion with the first output signal and controlling the solid state control portion with second output signal.

52. A method as recited in claim 50 wherein controlling the arc suppression circuit comprises providing coordinated operation of the arc suppression circuit to reduce the arc at the electrical contact with the first output signal and the second output signal.

53. A method as recited in claim 52 controlling a timing of the solid state control portion to be conducting when the electrical contact of the mechanical relay control portion is opened or closed with the first output signal and the second output signal.

54. A method as recited in claim 50 further comprising electrically isolating the first output signal from a mechanical relay within the mechanical relay control portion.

55. A method as recited in claim 50 further comprising electrically isolating the first output signal from a mechanical relay within the mechanical relay control portion with a light emitting diode and a phototransistor.

56. A method as recited in claim 50 further comprising electrically isolating the second output signal from a solid state device within the solid state control portion.

57. A method as recited in claim 48 further comprising electrically isolating the second output signal from a solid state device within the solid state control portion with a photo-triac.

58. A method as recited in claim 50 wherein generating a control output signal comprises generating the control output signal at a microprocessor and further comprising communicating between the microprocessor and a supervisory microprocessor through the serial communication link.

59. A method as recited in claim 58 further comprising isolating the microprocessor and the supervisory microprocessor using an isolation circuit disposed within the serial communication link.

60. A method as recited in claim 59 wherein the isolation circuit comprises a dual channel digital isolator.

61. A method as recited in claim 58 further comprising generating a serial output signal at the microprocessor through the serial communication link.

62. A method as recited in claim 61 wherein the serial output signal comprises an error signal.

63. A method as recited in claim 61 wherein the serial output signal comprises a status signal.

64. A method as recited in claim 61 wherein the serial output signal comprises a status signal corresponding to the status of the arc suppression circuit.