MEMORY SYSTEM

• US 20080250220A1
• Filed: 04/03/2008
• Published: 10/09/2008
• Est. Priority Date: 04/06/2007
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: ITO, Takafumi
• Application Number:
  US12/062,060
• Publication Number:
  US 20080250220A1
• Time in Patent Office: Days
• US Class Current: 711/173
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

In a memory system according to an aspect of the invention, a nonvolatile semiconductor memory includes storage areas each composed of a group of storage elements, stores one or more than one bit of data into each of the storage elements and selects either a first write mode in which n bits or a second write mode in which n+1 bits are stored into each of the storage elements. A controller instructs the semiconductor memory to store data, for each of logical address groups each composed of logical addresses belonging to a specific range, by writing a part of the data allocated with the logical addresses included in the logical address group into a first number of the storage areas in the first write mode and writing another part of the data into a second number of the storage areas in the second write mode.

Claims

1. A memory system comprising:

a nonvolatile semiconductor memory which includes a plurality of storage areas each composed of a group of a plurality of storage elements, stores one or more than one bit of data into each of the plurality of storage elements and selects either a first write mode in which n (n is a natural number) bits of data are stored into each of the plurality of storage elements or a second write mode in which n+1 or more bits of data are stored into each of the plurality of storage elements for each of the plurality of storage areas; and

a controller which instructs the nonvolatile semiconductor memory to store data, for each of a plurality of logical address groups each composed of a plurality of logical addresses belonging to a specific range, by writing a part of the data allocated with the logical addresses included in the logical address group into a preset first number of the plurality of storage areas in the first write mode and writing another part of the data into a preset second number of storage areas in the plurality of storage areas in the second write mode.

2. The memory system according to claim 1, wherein the nonvolatile semiconductor memory further carries out a first operation using a first combination of the first number and the second number or a second operation using a second combination of the first number and the second number;

outputs information about the performance based on the first operation and that based on the second operation; and

switches of switching between the first operation and the second operation under external control.

3. The memory system according to claim 1, wherein the first number and the second number are set so that the sum of the capacity of the plurality of storage areas written into in the first write mode and the capacity of the plurality of storage areas written into in the second write mode is greater than or equal to a specific storage capacity previously defined for the logical address group.

4. The memory system according to claim 3, wherein the first number and the second number are set so that an average write time required to write the data allocated to the logical addresses included in the logical address group is shorter than a specific preset write time.

5. The memory system according to claim 4, wherein, of the first number and the second number, the first number is set so as to be as large as possible.

6. The memory system according to claim 1, wherein the write speed in the first write mode is higher than the write speed in the second write mode.

7. The memory system according to claim 1, wherein the storage capacity of the logical address group is defined by the storage capacity of the nonvolatile semiconductor memory.

8. The memory system according to claim 1, wherein the controller includes an SD interface.

9. The memory system according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory.

10. A memory system comprising:

a nonvolatile semiconductor memory which includes a plurality of storage areas each composed of a group of a plurality of storage elements, stores one or more than one bit of data into each of the plurality of storage elements and selects either a first write mode in which n (n is a natural number) bits of data are stored into each of the plurality of storage elements or a second write mode in which n+1 or more bits of data are stored into each of the plurality of storage elements for each of the plurality of storage areas; and

a controller which instructs the nonvolatile semiconductor memory to store data, for each of a plurality of logical address groups each composed of a plurality of logical addresses belonging to a specific range, by writing a part of the data allocated with the logical addresses included in the logical address group into a preset first number of the plurality of storage areas in the first write mode and writing another part of the data into a preset second number of the plurality of storage areas in the second write mode,

wherein a first logical area with a first storage capacity and a second logical area with a second storage capacity are set, and

the plurality of storage areas are allocated to the logical address group in the first logical area and the logical address group in the second logical area in such a manner that the first number or the second number differs between the logical address group in the first logical area and that in the second logical area.

11. The memory system according to claim 10, wherein the first and second logical areas are set in one logical address space composed of the plurality of logical address groups.

12. The memory system according to claim 10, wherein the nonvolatile semiconductor memory further carries out a first operation using a first combination of the first number and the second number or a second operation using a second combination of the first number and the second number,

sets the first storage capacity and the second storage capacity,

defines one of the first and second operations for the first logical area and further defining the other of the first and second operations for the second logical area,

outputs information about the first storage capacity and second storage capacity and about the performance based on the operation defined for the first logical area and that based on the operation defined for the second logical area;

changes the first storage capacity or second storage capacity under external control; and

switches between the operation defined for the first logical area and the operation defined for the second logical area.

13. The memory system according to claim 10, wherein the nonvolatile semiconductor memory further outputs the begin address and end address of each of the first and second logical areas stored in the nonvolatile semiconductor memory.

14. The memory system according to claim 10, wherein the first number and the second number are set so that the sum of the capacity of the plurality of storage areas written into in the first write mode and the capacity of the plurality of storage areas written into in the second write mode is greater than or equal to a specific storage capacity previously defined for the logical address group.

15. The memory system according to claim 14, wherein the first number and the second number are set so that an average write time required to write the data allocated to the logical addresses included in the logical address group is shorter than a specific preset write time.

16. The memory system according to claim 15, wherein, of the first number and the second number, the first number is set so as to be as large as possible.

17. The memory system according to claim 10, wherein the write speed in the first write mode is higher than the write speed in the second write mode.

18. The memory system according to claim 10, wherein the storage capacity of the logical address group included in the first logical area is defined on the basis of the first storage capacity and the storage capacity of the logical address group included in the second logical area is defined on the basis of the second storage capacity.

19. The memory system according to claim 10, wherein the controller includes an SD interface.

20. The memory system according to claim 10, wherein the nonvolatile semiconductor memory is a NAND flash memory.