Wafer-level package having test terminal

• US 20080251788A1
• Filed: 06/10/2008
• Published: 10/16/2008
• Est. Priority Date: 12/28/1998
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Maruyama, Shigeyuki
• Granted Patent: US 7,642,551 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Claims

1. A wafer-level package comprising:

a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;

at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and

an excessive power supply protection element provided in said outer region and between said test chip terminal and said at least one testing member.

2. A wafer-level package comprising:

a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;

at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and

at least one common line provided in said outer region, a plurality of said redistribution traces extending out of a plurality of said semiconductor chip circuit forming regions being connected to said common line, wherein said at least one testing member includes a test pad provided at a part of said common line and exposed from said insulating material.

3. A wafer-level package comprising:

a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;

at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and

a plurality of units having different functions and provided within said semiconductor chip circuit forming region, a first end of said at least one redistribution trace being connected to one of, or combination of, said units, and a second end of said at least one redistribution trace being connected to said at least one testing member.

4. A wafer-level package comprising:

a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;

at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material;

a test history recording part provided in said outer region and connected to said second end of a plurality of said redistribution traces; and

input/output terminals for writing into/reading out from said test history recording part, said input/output terminals being exposed from said insulating material.

5. A wafer-level package comprising:

a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;

at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member;

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material; and

a common line in said outer region, a plurality of said redistribution traces extending out of a plurality of said semiconductor chip circuit forming region being connected to said common line,

wherein said at least one testing member includes a test supporting element provided at a part of said common line for testing said semiconductor chip circuit.

6. A wafer-level package comprising:

a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being connected to one of said test chip terminals and a second end of said redistribution trace being extended out to a position offset from said one of said chip terminals;

at least one testing member provided in an outer region of said semiconductor chip circuit forming region, said second end of said redistribution trace being connected to said least one testing member; and

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one testing member being exposed from said insulating material,

wherein said at least one testing member includes a plurality of test terminals provided with a predetermined rule in such a manner that said semiconductor wafer can be identified from said positions of said test terminals.