SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20080251839A1
• Filed: 08/28/2007
• Published: 10/16/2008
• Est. Priority Date: 04/12/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: LEE, Sang Don
• Granted Patent: US 7,816,730 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si_1-xGe_x) layer for fill the recess (where 0<X<1 and X is a Ge mole fraction).

Claims

1. A semiconductor device comprising:

a fin-type active region defined on a semiconductor substrate having a device isolation structure;

a recess formed over the fin-type active region; and

a gate electrode formed over the fin-type active region to fill the recess, the gate electrode including a silicon germanium layer.

2. The semiconductor device of claim 1, further comprising a lightly doped drain (“

LDD”

) region on the semiconductor substrate disposed at both sides of the gate electrode.

3. The semiconductor device of claim 2, wherein the gate electrode includes an upper gate electrode and a lower gate electrode, the lower gate electrode including a stacked structure of a p+ polysilicon layer and a p+ polysilicon germanium layer.

4. The semiconductor device of claim 3, wherein a thickness of the p+ polysilicon germanium layer is at least equal to a depth of the LDD region.

5. A method for fabricating a semiconductor device, the method comprising:

forming a device isolation structure on a semiconductor substrate to define an active region;

selectively etching a portion of the device isolation structure to form a fin-type active region; and

forming a gate structure over the fin-type active region, the gate structure including a layer which includes silicon germanium.

6. The method of claim 5, wherein the step of forming the fin-type active region comprises:

forming a hard mask layer over the semiconductor substrate;

forming a photoresist pattern over the hard mask layer to define a recess gate region;

selectively etching the hard mask layer and the device isolation structure by using the photoresist pattern as an etching mask to form a recess exposing the fin-type active region; and

removing the photoresist pattern and the hard mask layer to expose the active region including the fin-type active region.

7. The method of claim 5, further comprising performing a soft etching process on the fin-type active region.

8. The method of claim 5, wherein the step of forming the gate structure comprises:

forming a lower gate conductive layer including the layer over the semiconductor substrate;

forming an upper gate conductive layer and a gate hard mask layer over the lower gate conductive layer; and

patterning the gate hard mask layer, the upper gate conductive layer, and the lower gate conductive layer to form the gate structure.

9. The method of claim 8, wherein the step of forming the lower gate conductive layer comprises:

forming a polysilicon layer over the semiconductor substrate; and

injecting impurity ions including Ge into the polysilicon layer to form the layer.

10. The method of claim 9, further comprising performing a thermal treatment process on the semiconductor substrate, so that the lower gate conductive layer defines the polysilicon layer and the layer provided over the polysilicon layer.

11. The method of claim 8, wherein the step of forming the lower gate conductive layer comprises:

forming a polysilicon layer over the semiconductor substrate;

forming a layer which includes silicon germanium over the polysilicon layer; and

performing a thermal treatment process on the semiconductor substrate to drive dopants in the layer.

12. The method of claim 11, wherein forming the layer includes depositing a silicon layer doped with germanium, wherein the thermal treatment drives the dopants of the silicon layer into the polysilicon layer to expand the layer into the polysilicon layer.

13. The method of claim 11, wherein forming the layer includes implanting dopants into the polysilicon layer.

14. The method of claim 8, wherein the step of forming the lower gate conductive layer comprises:

forming a first p+ polysilicon layer over the semiconductor substrate;

forming a p+ polysilicon germanium layer over the first p+ polysilicon layer;

forming a second p+ polysilicon layer over the p+ polysilicon germanium layer; and

performing a thermal treatment process on the semiconductor substrate to form a stacked structure of the p+ polysilicon layer and the p+ polysilicon germanium layer.

15. The method of claim 5, further comprising forming a gate insulating film over the active region including the fin-type active region.

16. The method of claim 5, further comprising forming a LDD region on the semiconductor substrate at both sides of the gate structure.

17. The method of claim 16, wherein a thickness of the layer is at least equal to the depth of the LDD region.

18. A method for fabricating a semiconductor device, the method comprising:

forming a device isolation structure on a semiconductor substrate to define an active region;

etching a portion of the device isolation structure to form a fin-type active region; and

forming a gate structure over the fin-type active region, the gate structure including a polysilicon layer, a doped polysilicon layer over the polysilicon layer, and a gate conductive layer over the doped polysilicon layer, the gate conductive layer including metal.

19. The method of claim 18, wherein the doped polysilicon layer is a layer which includes silicon germanium, wherein a lower surface of the doped polysilicon layer is provided below an upper surface of the fin-type active region.

20. The method of claim 19, wherein the doped polysilicon is formed by implanting dopants into the polysilicon layer and performing a thermal treatment of the substrate.